參數(shù)資料
型號： AD7805BNZ
廠商： Analog Devices Inc
文件頁數(shù)： 11/28頁
文件大?。?/td> 0K
描述： IC DAC 10BIT QUAD PARALLEL 28DIP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 13
設(shè)置時間： 1.5µs
位數(shù)： 10
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 66mW
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 28-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 28-PDIP
包裝： 管件
輸出數(shù)目和類型： 8 電壓，雙極
采樣率（每秒）： 667k
AD7804/AD7805/AD7808/AD7809
–19–
REV. A
Table IX. Offset Binary Code Table for Sub DAC
Digital Input
Analog Output
MSB . . . LSB
11111111
VBIAS/16
× 127/256
11111110
VBIAS/16
× 126/256
10000001
VBIAS/16
× 1/256
10000000
0
01111111
–VBIAS/16
× 1/256
00000001
–VBIAS/16
× 127/256
00000000
–VBIAS/32
127
VBIAS
128
32
VBIAS
32
0
DAC
OUTPUT
VOLTAGE
00
01
DAC INPUT CODE
7F
80
81
FE
FF
Figure 26. Sub DAC Output Voltage vs. DAC Input Codes
(HEX) for Offset Binary Coding
Configuring the AD7804/AD7808 for Offset Binary Coding
Figure 27 shows a typical configuration for the AD7804/AD7808.
This circuit can be used for both 3.3 V or 5 V operation and
uses an external AD589 as the reference for the part and serial
interfacing with offset binary coding is used. The MX1 and
MX0 bits in the system control register have to be set to enable
selection of the AD589 as the reference. The following are the
steps required to operate the DACs in this part. Figures 4 to 7
show the contents of the registers on the AD7804/AD7808.
AD589
0.01 F
AD7804/
AD7808
AVDD
DVDD
VOUTA
VOUTB
VOUTC
VOUTD
AGND
DGND
LDAC
CLR
COMP
SDIN
FSIN
DVDD
REFIN
REFOUT
0.1 F
10 F
0.01 F
SERIAL
INTERFACE
+3.3V/+5V
6.8k
CLKIN
Figure 27. Typical Configuration for AD7804/AD7808
Using an AD589 1.23 V Reference for the AD7804/AD7808
System Control Register Serial Write:
Write 0060 Hex
Mode bits select system control register
and configure system for offset binary
coding and normal operation.
Channel Control Register Serial Write:
Write 4210 Hex
Mode bits select channel control register,
channel A is configured for operation with
external reference.
Main DAC Data Register Serial Write:
Write 23FF Hex
This 16-bit write selects writing to channel
A and writes full scale to the Main DAC.
Sub DAC Data Register Serial Write:
Write A3FF Hex
This 16-bit write selects writing to channel
A Sub DAC and writes full scale to the
Sub DAC.
Table VIII and Figure 25 show the analog outputs available for
the above configuration when writing to the Main DAC only
while Table IX and Figure 26 show the contributions from the
Sub DAC to the overall transfer function. The total output for a
single channel when using offset binary coding is the sum of that
from the Main DAC and the Sub DAC.
VOUT = VOUT' + VOUT"
= VBIAS + 1.875
× V
BIAS
× ((NA-512)/1024) + V
BIAS/16
=
× [(NB-128)/256]
= VBIAS
× (1 + 1.875 × ((NA-512)/1024) + (NB-128)/
4096)
where NA ranges from 0 to +1023 and NB ranges from 0 to
+255. Figure 28 shows a pictorial view of the transfer function
for any DAC channel.
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