參數(shù)資料
型號： AD7808
廠商： Analog Devices, Inc.
英文描述： +3.3 V to +5 V Quad/Octal 10-Bit DACs
中文描述： 3.3伏至5伏四/八通道10位DAC
文件頁數(shù)： 14/28頁
文件大?。?/td> 300K
代理商： AD7808
AD7804/AD7805/AD7808/AD7809
REV. A
–14–
Table IVb. AD7809 DAC Data/Control Register
Selection Table
MODE
A2
A1
A0
Function Selected
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAC A Control Register
DAC B Control Register
DAC C Control Register
DAC D Control Register
DAC E Control Register
DAC F Control Register
DAC G Control Register
DAC H Control Register
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAC A Data Register
DAC B Data Register
DAC C Data Register
DAC D Data Register
DAC E Data Register
DAC F Data Register
DAC G Data Register
DAC H Data Register
AD7805/AD7809 SYSTEM OR CHANNEL CONTROL
REGISTER SELECTION
MD0
0
This enables writing to the system control register.
The contents of this are shown in Figure 12. Mode
must be low to access this control register.
This enables writing to the channel control register.
The contents of this are shown in Figure 13. Mode
must also be low to access this control register.
1
AD7805/AD7809 SYSTEM CONTROL REGISTER
The bits in this register allow control over all DACs in the pack-
age. The control bits include data format (
10
/8), power down
(
PD
), DAC input coding select (BIN/
COMP
), system standby
(SSTBY) and a system clear (SCLR). The function of these bits
is as follows:
Data Format
10
/8
0
10-bit parallel loading structure.
1
Byte loading structure
.
(8+2 loading)
.
Input Coding
BIN/
COMP
0
Twos complement coding.
1
Offset Binary Coding.
Power Down
PD
0
Complete power-down of device.
1
Normal operation (default on power-up).
System Standby
SSTBY
0
Normal operation.
1
All DACs in the package put in standby mode (default
on power-up).
System Clear
SCLR
0
1
Normal operation.
All DACs in the package are cleared to a known state
depending on the coding scheme selected. The SCLR bit
clears the Main DACs only; the Sub DACs are unaf-
fected by the system clear function. The main DAC is
cleared to different levels depending on the coding
scheme. With offset binary coding the Main DAC output
is cleared to the bottom of the transfer function V
BIAS
/16.
With twos complement coding the Main DAC output is
cleared to midscale V
BIAS
. The channel output will be the
sum of the Main DAC and Sub DAC contributions.
AD7805/AD7809 CHANNEL CONTROL REGISTER
This register allows the user to have control over individual
DACs in the package. The control bits in this register include
multiplexer output selection (MX1 and MX0), Main or Sub
DAC selection (
MAIN
/SUB), standby (
STBY
) and individual
DAC clear (CLR). The function of these bits is as follows.
Multiplexer Selection (MX1, MX0)
Table V shows the V
BIAS
selection using MX1 and MX0 bits in
the channel control register.
Table V. V
BIAS
Selection Table
MX1
0
0
1
1
MX0
0
1
0
1
V
BIAS
V
DD
/2 (Default on Power-Up)
INTERNAL VREF
REFIN
Undetermined
Main DAC or Sub DAC Selection
MAIN
/SUB
0
Writing a 0 to this bit means that the data in the next
data register write is transferred to the selected Main
DAC.
1
Writing a 1 to this bit means that the data in the next
data register write is transferred to the selected Sub DAC.
This applies to the 10-bit parallel load feature. In byte
load mode, (Figure 15) DB0 selects the Main or Sub
DAC data registers.
Standby
STBY
0
Places the selected DAC and its associated linear cir-
cuitry in Standby Mode.
1
Normal operation (default on power-up).
Clear
CLR
0
Normal operation.
1
Clears the output of the selected Main DAC to one
of two conditions depending on the input coding se-
lected. With offset binary coding the Main DAC out-
put is cleared to the bottom of the transfer function,
V
BIAS
/16 and with twos complement coding the Main
DAC output is cleared to midscale V
BIAS
. The Sub
DAC is unaffected by a clear operation. An
LDAC
signal has to be applied to the DAC for a channel clear
to be implemented.
相關(guān)PDF資料
PDF描述
AD7809 +3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7804 +3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7804BN ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
AD7804BR +3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7805BN %2B3.3V to %2B5V Quad/Octal 10-Bit DACs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7808BN 制造商:Analog Devices 功能描述:DAC 8-CH 10-bit 24-Pin PDIP Tube 制造商:Analog Devices 功能描述:10BIT DAC OCTAL SERIAL 7808 DIP24
AD7808BNZ 功能描述:IC DAC 10BIT OCTAL SERIAL 24DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:*
AD7808BNZ 制造商:Analog Devices 功能描述:10BIT DAC OCTAL SERIAL 7808 DIP24
AD7808BR 功能描述:IC DAC 10BIT 3.3V OCTAL 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
AD7808BR-REEL 功能描述:IC DAC 10BIT OCTAL SRL 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
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