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參數(shù)資料
| 型號(hào)： | AD7809BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT OCTAL PARALL 44TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時(shí)間： | 1.5µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 99mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，雙極 |
| 采樣率（每秒）： | 667k |
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AD7804/AD7805/AD7808/AD7809
–7–
REV. A
AD7804/AD7808 PIN FUNCTION DESCRIPTION
AD7804
AD7808
Pin No.
Mnemonic
Description
1
1, 6
AGND
Ground reference point for analog circuitry.
2, 3
VOUTB, VOUTA
Analog output voltage from the DACs.
4
REFOUT
Reference Output. This is a bandgap reference and is typically 1.23 V.
5
PD
Active low input used to put the part into low power mode reducing current consumption
to 1
A.
7, 8
VOUTF, VOUTE
Analog output voltages from the DACs.
59
FSIN
Level-triggered control input (active low). This is the frame synchronization signal for the
input data. When
FSIN goes low, it enables the input shift register and data is transferred
on the falling edges of CLKIN.
610
LDAC
LDAC Input. When this digital input is taken low, all DAC registers are simultaneously
updated with the contents of the data registers. If
LDAC is tied permanently low, or is
low on the sixteenth falling clock edge with timing similar to that of SDIN, an automatic
update will take place.
7
11
SDIN
Serial Data Input. These devices accept a 16-bit word. Data is clocked into the input shift
register on the falling edge of CLKIN.
8
12
DGND
Ground reference point for digital circuitry.
913
DVDD
Digital Power Supply.
10
14
CLKIN
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.
Duty Cycle should be between 40% and 60%.
11
15
CLR
Asynchronous
CLR Input. When this input is taken low, all Main DAC outputs are
cleared either to VBIAS or to VBIAS/16 volts. All Sub DACs are also cleared and thus the
transfer function of the Main DAC will remain centered around the VBIAS point.
16
NC
No Connect. This pin should be left open circuit.
17, 18
VOUTH, VOUTG
Analog output voltages from the DACs.
12
20
REFIN
This is an external reference input for the DACs. When this reference is selected for a
DAC in the control register, the analog output from the selected DAC swings around this
point.
13
21
COMP
Compensation Pin. This pin provides an output from the internal VDD/2 divider and is
provided for ac bypass purposes only. This pin should be decoupled with 1 nF capacitors
to both AVDD and AGND. This pin can be overdriven with an external reference, thus
giving the facility for two external references on the part.
14, 15
22, 23
VOUTD, VOUTC
Analog output voltage from the DACs.
16
19, 24
AVDD
Analog Power Supply. +3.3 V to +5 V.
AD7804 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AGND
VOUTB
VOUTA
REFOUT
FSIN
LDAC
SDIN
DGND
AVDD
VOUTC
VOUTD
COMP
REFIN
CLR
CLKIN
DVDD
AD7804
AD7808 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7808
NC = NO CONNECT
DGND
SDIN
LDAC
FSIN
VOUTE
AGND
VOUTB
VOUTA
REFOUT
VOUTF
AGND
PD
DVDD
CLKIN
CLR
NC
VOUTH
AVDD
VOUTC
VOUTD
COMP
VOUTG
AVDD
REFIN
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