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| 型號(hào)： | AD7827BRZ-REEL7 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SAMPLING SRL 8SOIC |
| 產(chǎn)品變化通告： | AD7827 Series Discontinuation 18/Jul/2012 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)單端，單極 |
AD7827
–11–
REV. 0
MICROPROCESSOR INTERFACING
The Serial Interface on the AD7827 allows the part to be con-
nected directly to a range of many different microprocessors and
microcontrollers. This section explains how to interface the
AD7827 with some of the more common DSP serial interface
protocols.
AD7827 to TMS320C5x
The serial interface on the TMS320C5x uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices such as the AD7827.
A receive frame synchronization output has been supplied on
the AD7827 to allow easy interfacing with no extra gluing logic.
The serial port of the TMS320C5x is set up to operate in Burst
Mode with internal CLKX (TX serial clock) and FSR (RX
frame sync). The Serial Port Control register (SPC) must have
the following setup: F0 = 1, FSM = 1, MCM = 1. The connec-
tion diagram is shown in Figure 16.
TMS320C5x*
CLKX
CLKR
DR
FSR
AD7827*
SCLK
DOUT
RFS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. Interfacing to the TMS320C5x
AD7827 to ADSP-21xx
The ADSP-21xx family of DSPs are easily interfaced to the
AD7827 without the need for any extra gluing logic. The
SPORT is operated in alternate framing mode. The SPORT
control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 0111, 8-Bit Data Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, External Framing Signal
ITFS = 1, Internal Framing Signal
The 8-bit data words will be right justified in the 16-bit serial
data registers when using this configuration. Figure 17 shows
the connection diagram.
ADSP-21xx*
DR
AD7827*
SCLK
DOUT
RFS
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Interfacing to the ADSP-21xx
AD7827 to DSP56xxx
The connection diagram in Figure 18 shows how the AD7827
can be connected to the SSI (Synchronous Serial Interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is oper-
ated in Synchronous Mode (SYN bit in CRB = 1) with inter-
nally generated 1-bit clock period frame sync for both TX and
RX (FSL1 and FSL0 bits in CRB = 1 and 0 respectively).
DSP56xxx*
SRD
AD7827*
SCLK
DOUT
SC2
RFS
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. Interfacing to the DSP56xxx
Microcontrollers
The AD7827 may also be interfaced to many microcontrollers,
as a continuous serial clock is not essential. However, enough
time must be left for the conversion to be complete before
applying a burst of serial clocks to read out the data.
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