- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8580 > AD7840KPZ (Analog Devices Inc)IC DAC 14BIT LOW PWR 5V 28-PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7840KPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT LOW PWR 5V 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 2.5µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 400k |
AD7840
REV. B
–10–
MICROPROCESSOR INTERFACING
The AD7840 logic architecture allows two interfacing options
for interfacing the part to microprocessor systems. It offers a
14-bit wide parallel format and a serial format. Fast pulse
widths and data setup times allow the AD7840 to interface
directly to most microprocessors including the DSP processors.
Suitable interfaces to various microprocessors are shown in
Figures 15 to 23.
Parallel Interfacing
Figures 15 to 17 show interfaces to the DSP processors, the
ADSP-2100, the TMS32010 and TMS32020. An external
timer controls the updating of the AD7840. Data is loaded to
the AD7840 input latch using the following instructions:
ADSP-2100: DM(DAC) = MR0
TMS32010: OUT DAC,D
TMS32020: OUT DAC,D
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
DAC = AD7840 Address
Figure 15. AD7840–ADSP-2100 Parallel Interface
Figure 16. AD7840–TMS32010 Parallel Interface
Figure 17. AD7840–TMS32020 Parallel Interface
Some applications may require that the updating of the AD7840
DAC latch be controlled by the microprocessor rather than the
external timer. One option (for double-buffered interfacing) is
to decode the AD7840 LDAC from the address bus so that a
write operation to the DAC latch (at a separate address than the
input latch) updates the output. An example of this is shown in
the 8086 interface of Figure 18. Note that connecting the
LDAC
input to the CS input will not load the DAC latch cor-
rectly since both latches cannot he transparent at the same time.
AD7840–8086 Interface
Figure 18 shows an interface between the AD7840 and the 8086
microprocessor. For this interface, the LDAC input is derived
from a decoded address. If the least significant address line, A0,
is decoded then the input latch and the DAC latch can reside at
consecutive addresses. A move instruction loads the input latch
while a second move instruction updates the DAC latch and the
AD7840 output. The move instruction to load a data word
WXYZ to the input latch is as follows:
MOV DAC,#YZWX
DAC = AD7840 Address
Figure 18. AD7840–8086 Parallel Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B63-MY-B1 | CONVERTER MOD DC/DC 24V 50W |
| VI-B62-MY-B1 | CONVERTER MOD DC/DC 15V 50W |
| VI-2WK-IV-F3 | CONVERTER MOD DC/DC 40V 150W |
| VI-B4X-MY-B1 | CONVERTER MOD DC/DC 5.2V 50W |
| VI-B4W-MY-B1 | CONVERTER MOD DC/DC 5.5V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7840KPZ-RL | 功能描述:14 Bit Digital to Analog Converter 1 28-PLCC (11.51x11.51) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 位數(shù):14 數(shù)模轉(zhuǎn)換器數(shù):1 建立時(shí)間:4μs 輸出類型:Voltage - Buffered 差分輸出:無 數(shù)據(jù)接口:并聯(lián)，串行 參考類型:外部， 內(nèi)部 電壓 - 電源，模擬:±5V 電壓 - 電源，數(shù)字:- INL/DNL（LSB）:±1（最大），±0.9（最大） 架構(gòu):R-2R 工作溫度:0°C ~ 70°C 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商器件封裝:28-PLCC（11.51x11.51） 標(biāo)準(zhǔn)包裝:1 |
| AD7840LN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:14-Bit Digital-to-Analog Converter |
| AD7840LP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:14-Bit Digital-to-Analog Converter |
| AD7840SE/883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:14-Bit Digital-to-Analog Converter |
| AD7840SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete 14-Bit DAC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。