參數(shù)資料
型號(hào): AD7846JPZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 7/24頁
文件大?。?/td> 0K
描述: IC DAC 16BIT MONO V-OUT 28-PLCC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 750
設(shè)置時(shí)間: 7µs
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
功率耗散(最大): 100mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 143k
AD7846
Rev. G | Page 15 of 24
POSITION MEASUREMENT APPLICATION
Figure 25 shows the AD7846 in a position measurement applica-
tion using an linear variable displacement transducer (LVDT),
an AD630 synchronous demodulator and a comparator to make
a 16-bit LVDT-to-digital converter. The LVDT is excited with a
fixed frequency and fixed amplitude sine wave (usually 2.5 kHz,
2 V p-p). The outputs of the secondary coil are in antiphase and
their relative amplitudes depend on the position of the core in the
LVDT. The AD7846 output interpolates between these two inputs
in response to the DAC input code. The AD630 is set up so that
it rectifies the DAC output signal. Thus, if the output of the DAC is
in phase with the VREF+ input, the inverting input to the compara-
tor is positive, and if it is in phase with VREF, the output is nega-
tive. By turning on each bit of the DAC in succession starting
with the MSB and deciding to leave it on or turn it off based on
the comparator output, a 16-bit measurement of the core position
is obtained.
AD7846*
LVDT
DB0
DB15
R1
100k
C1
1F
PROCESSOR DATA BUS
SIGNAL
GROUND
TO
PROCESSOR PORT
*ADDITIONAL PINS OMITTED FOR CLARITY
x ASIN ω t
–(1–x) ASIN ω t
ASIN ω t
AD630*
DGND
VOUT
RIN
VREF+
VREF–
6
20
7
5
8
10
13
10
9
16
3
08
49
0-
02
7
Figure 25. AD7846 in Position Measurement Application
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