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| 型號(hào)： | AD7862BRZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT DUAL 250KSPS 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 75mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 4 個(gè)單端，雙極 |
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AD7862
–13–
REV. 0
MICROPROCESSOR INTERFACING
The AD7862 high speed bus timing allows direct interfacing to
DSP processors as well as modern 16-bit microprocessors.
Suitable microprocessor interfaces are shown in Figures 14
through 18.
AD7862–ADSP-2100 Interface
Figure 14 shows an interface between the AD7862 and the
ADSP-2100. The CONVST signal can be supplied from the
ADSP-2100 or from an external source. The AD7862 BUSY
line provides an interrupt to the ADSP-2100 when conversion is
completed on all four channels. The four conversion results can
then be read from the AD7862 using four successive reads to
the same memory address. The following instruction reads one
of the four results (this instruction is repeated four times to read
all four results in sequence):
MR0 = DM(ADC)
where MR0 is the ADSP-2100 MR0 register, and ADC is the
AD7862 address.
OPTIONAL
DMA0
DMA13
DMD15
DMD0
DMS
EN
ADDR
DECODE
ADDRESS BUS
ADSP-2100
(ADSP-2101/
ADSP-2102)
* ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
CONVST
CS
DB11
DB0
RD
BUSY
AD7862*
IRQn
DMRD (RD)
A0
Figure 14. AD7862–ADSP-2100 Interface
AD7862–ADSP-2101/ADSP-2102 INTERFACE
The interface outlined in Figure 14 also forms the basis for an
interface between the AD7862 and the ADSP-2101/ADSP-2102.
The READ line of the ADSP-2101/ADSP-2102 is labeled RD.
In this interface, the RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Register.
The instruction used to read one of the four results is outlined
for the ADSP-2100.
AD7862–TMS32010 Interface
An interface between the AD7862 and the TMS32010 is shown
in Figure 15. Once again, the CONVST signal can be supplied
from the TMS32010 or from an external source, and the
TMS32010 is interrupted when both conversions have been
completed. The following instruction is used to read the conver-
sion results from the AD7862:
IN D,ADC
where D is Data Memory address, and ADC is the AD7862
address.
OPTIONAL
PA0
PA2
D15
D0
MEN
EN
ADDR
DECODE
ADDRESS BUS
TMS32010
* ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
CONVST
CS
DB11
DB0
RD
BUSY
AD7862*
INT
DEN
A0
Figure 15. AD7862–TMS32010 Interface
AD7862–TMS320C25 Interface
Figure 16 shows an interface between the AD7862 and the
TMS320C25. As with the two previous interfaces, conversion
can be initiated from the TMS320C25 or from an external
source, and the processor is interrupted when the conversion
sequence is completed. The TMS320C25 does not have a
separate RD output to drive the AD7862 RD input directly.
This has to be generated from the processor STRB and R/W
outputs with the addition of some logic gates. The RD signal is
OR-gated with the MSC signal to provide the one WAIT state
required in the read cycle for correct interface timing. Conver-
sion results are read from the AD7862 using the following
instruction:
IN D,ADC
where D is Data Memory address and ADC is the AD7862
address.
A0
A15
D15
D0
IS
EN
ADDR
DECODE
ADDRESS BUS
OPTIONAL
DATA BUS
CONVST
CS
DB11
DB0
RD
BUSY
AD7862*
TMS320C25
*ADDITIONAL PINS OMITTED FOR CLARITY
INTn
R/W
STRB
MSC
READY
A0
Figure 16. AD7862–TMS320C25 Interface
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