參數(shù)資料
型號： AD7873ARUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 15/29頁
文件大小： 0K
描述： IC ADC 12BIT TOUCHSCREEN 16TSSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： 電阻
觸摸面板接口： 4 線
輸入數(shù)/鍵： 1 TSC
分辨率（位）： 12 b
評估套件： 可供
數(shù)據(jù)接口： 串行
數(shù)據(jù)速率/采樣率 (SPS，BPS)： 125k
電壓基準(zhǔn)： 外部，內(nèi)部
電源電壓： 2.2 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
Data Sheet
AD7873
Rev. F | Page 21 of 28
SERIAL INTERFACE
Figure 36 shows the typical operation of the serial interface of
the AD7873. The serial clock provides the conversion clock and
also controls the transfer of information to and from the AD7873.
One complete conversion can be achieved with 24 DCLK cycles.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS takes the BUSY output and the serial bus
out of three-state. The first eight DCLK cycles are used to write
to the control register via the DIN pin. The control register is
updated in stages as each bit is clocked in. Once the converter
has enough information about the following conversion to set
the input multiplexer and switches appropriately, the converter
enters the acquisition mode and, if required, the internal switches
are turned on. During acquisition mode, the reference input
data is updated. After the three DCLK cycles of acquisition, the
control word is complete (the power management bits are now
updated) and the converter enters conversion mode. At this
point, track-and-hold goes into hold mode, the input signal is
sampled, and the BUSY output goes high (BUSY returns low on
the next falling edge of DCLK). The internal switches can also
turn off at this point if in single-ended mode, battery-monitor
mode, or temperature measurement mode.
The next 12 DCLK cycles are used to perform the conversion
and to clock out the conversion result. If the conversion is
ratiometric (SER/DFR low), the internal switches are on during
the conversion. A 13th DCLK cycle is needed to allow the
DSP/micro to clock in the LSB. Three more DCLK cycles clock
out the three trailing zeros and complete the 24 DCLK transfer.
The 24 DCLK cycles can be provided from a DSP or via three
bursts of eight clock cycles from a microcontroller.
Figure 36. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.
Figure 37. Detail Timing Diagram
DCLK
DIN
BUSY
DOUT
X/Y SWITCHES1
(SER/DFR HIGH)
X/Y SWITCHES1, 2
(SER/DFR LOW)
THREE-STATE
(START)
IDLE
OFF
(MSB)
(LSB)
ON
OFF
ACQUIRE
CONVERSION
IDLE
ZERO FILLED
THREE-STATE
tACQ
1
8
11
10
9
8
7
6
5
4
3
2
1
0
1
S
A2
PD1 PD0
A1
A0 MODE
SER/
DFR
NOTES
1Y DRIVERS ARE ON WHEN X+ IS SELECTED INPUT CHANNEL (A2 TO A0 = 001); X DRIVERS ARE ON WHEN Y+ IS SELECTED INPUT CHANNEL (A2 TO A0 = 101).
WHEN PD1, PD0 = 00, 01 OR 10, Y– WILL TURN ON AT THE END OF THE CONVERSION.
2DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE,
OR POWER-DOWN MODE IS CHANGED, OR CS IS HIGH.
CS
02164-
036
CS
DCLK
DIN
BUSY
DOUT
DB11
PD0
DB10
t1
t4
t5
t6
t9
t10
t11
t7
t2
t3
t8
t12
02164-
037
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