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參數(shù)資料
| 型號(hào)： | AD7873ARUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT TOUCHSCREEN 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 電阻 |
| 觸摸面板接口： | 4 線 |
| 輸入數(shù)/鍵： | 1 TSC |
| 分辨率（位）： | 12 b |
| 評(píng)估套件： | 可供 |
| 數(shù)據(jù)接口： | 串行 |
| 數(shù)據(jù)速率/采樣率 (SPS，BPS)： | 125k |
| 電壓基準(zhǔn)： | 外部，內(nèi)部 |
| 電源電壓： | 2.2 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD7873
Rev. F | Page 5 of 28
TIMING SPECIFICATIONS
TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 5.25 V, VREF = 2.5 V.
Parameter
Limit at TMIN, TMAX
Unit
Description
10
kHz min
2
MHz max
tACQ
1.5
s min
Acquisition time
t1
10
ns min
CS falling edge to first DCLK rising edge
t2
60
ns max
CS falling edge to busy three-state disabled
60
ns max
CS falling edge to DOUT three-state disabled
t4
200
ns min
DCLK high pulse width
t5
200
ns min
DCLK low pulse width
t6
60
ns max
DCLK falling edge to BUSY rising edge
t7
10
ns min
Data setup time prior to DCLK rising edge
t8
10
ns min
Data valid to DCLK hold time
200
ns max
Data access time after DCLK falling edge
t10
0
ns min
CS rising edge to DCLK ignored
t11
100
ns max
CS rising edge to BUSY high impedance
100
ns max
CS rising edge to DOUT high impedance
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the DCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.
4
t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Figure 2. Load Circuit for Digital Output Timing Specifications
200A
IOL
200A
IOH
1.6V
TO OUTPUT
PIN
CL
50pF
02164-
002
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