參數(shù)資料
型號： AD7875LPZ
廠商： Analog Devices Inc
文件頁數(shù)： 11/28頁
文件大小： 0K
描述： IC ADC 12BIT SAMPLING 5V 28-PLCC
產(chǎn)品變化通告： Conversion Time Change
標準包裝： 1
位數(shù)： 12
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 95mW
電壓電源： 雙 ±
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 管件
輸入數(shù)目和類型： 1 個單端，單極
AD7870/AD7875/AD7876
Rev. C | Page 19 of
28
MICROPROCESSOR INTERFACE
The AD7870/AD7875/AD7876 have a wide variety of
interfacing options. They offer two operating modes and
three data-output formats. Fast data access times allow
direct interfacing to most microprocessors including the
DSP processors.
PARALLEL READ INTERFACING
Figure 22, Figure 23, and Figure 24 show interfaces to the
ADSP-2100, TMS32010 and the TMS32020 DSP processors.
The ADC is operating in Mode 1, parallel read for all three
interfaces. An external timer controls conversion start asyn-
chronously to the microprocessor. At the end of each conversion
the ADC BUSY/INT interrupts the microprocessor. The
conversion result is read from the ADC with the following
instruction:
ADSP-2100: MR0 = DM(ADC)
TMS32010: IN D,ADC
TMS32020: IN D,ADC
MR0 = ADSP-2100 MR0 Register
D = Data Memory Address
ADC = AD7870/AD7875/AD7876 Address
Some applications may require that conversions be initiated by
the microprocessor rather than an external timer. One option
is to decode the CONVST signal from the address bus so that a
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described earlier. Note: a read
operation must not be attempted during conversion.
DMA13
DMA0
CONVST
TIMER
CS
5V
12/8/CLK
BUSY/INT
RD
DB11
DB0
1ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDR
DECODE
EN
DMS
IRQn
DMRD
DMD15
DMD0
AD7870/
AD7875/
AD78761
ADSP-2100
07
73
0-
0
22
Figure 22. ADSP-2100 Parallel Interface
PA2
PA0
CONVST
TIMER
CS
5V
12/8/CLK
BUSY/INT
RD
DB11
DB0
1ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDR
DECODE
EN
MEN
INT
DEN
D15
D0
AD7870/
AD7875/
AD78761
TMS32010
07
73
0-
0
23
Figure 23. TMS32010 Parallel Interface
A15
A0
CONVST
TIMER
CS
5V
12/8/CLK
BUSY/INT
RD
DB11
DB0
ADDRESS BUS
DATA BUS
ADDR
DECODE
EN
IS
INTn
STRB
D15
D0
R/W
TMS32020
07
73
0-
0
24
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD7870/
AD7875/
AD78761
Figure 24. TMS32020 Parallel Interface
TWO-BYTE READ INTERFACING
68008 Interface
Figure 25 shows an 8-bit bus interface for the MC68008 micro-
processor. For this interface, the 12/8/CLK input is tied to 0 V
and the DB11/HBEN pin is driven from the microprocessor
least significant address bit. Conversion start control is provided
by the microprocessor. In this interface example, a Move instruc-
tion from the ADC address both starts a conversion and reads
the conversion result.
MOVEW ADC,DO
ADC = AD7870/AD7875/AD7876 address
D0 = 68008 D0 register
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