參數(shù)資料
型號： AD7875LPZ
廠商： Analog Devices Inc
文件頁數(shù)： 7/28頁
文件大小： 0K
描述： IC ADC 12BIT SAMPLING 5V 28-PLCC
產(chǎn)品變化通告： Conversion Time Change
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 100k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 95mW
電壓電源： 雙 ±
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 管件
輸入數(shù)目和類型： 1 個單端，單極
AD7870/AD7875/AD7876
Rev. C | Page 15 of
28
CONVST
TRACK-AND-HOLD
GOES INTO HOLD
TRACK-AND-HOLD RETURNS
TO TRACK AND
ACQUISITION TIME BEGINS
THREE-STATE
VALID
DATA
DB11 TO DB0
CS
RD
INT
DATA
t2
t1
tCONVERT
t5
t4
t7
t4
t3
07
73
0-
01
4
Figure 14. Mode 1 Timing Diagram, 12-Bit Parallel Read
CONVST
CS
RD
INT
SSTRB2
DATA
SCLK3
TRACK-AND-HOLD RETURNS TO TRACK
AND ACQUISITION TIME BEGINS
TRACK-AND-HOLD GOES INTO HOLD
THREE-STATE
LEADING
ZEROS
VALID
DATA
DB7 TO DB0
VALID
DATA
DB11 TO DB8
HBEN1
t1
SDATA2
1TIMES
t2, t3, t4, t8, AND t9 ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
2EXTERNAL 4.7k PULL-UP RESISTOR.
3EXTERNAL 2k PULL-UP RESISTOR;
CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK = –5V;
NONCONTINUOUS WHEN 12/8/CLK = 0V.
DB11
DB10
SERIAL DATA
DB0
t8
t2
t4
t3
t9
t7
t5
tCONVERT
t6
t11
t10
t12
t13
07
73
0-
0
15
t14
Figure 15. Mode 1 Timing Diagram, Byte or Serial Read
The Mode 1 timing diagram for byte and serial data is shown
in Figure 15. INT goes low at the end of conversion and is reset
high by the first falling edge of CS and RD. This first read at the
end of conversion can either access the low byte or high byte of
data depending on the status of HBEN (
shows low
byte only for example). The diagram shows both a nonconti-
nuously and a continuously running clock (dashed line).
MODE 2 INTERFACE
The second interface mode is achieved by hard wiring
CONVST low and conversion is initiated by taking CS low
while HBEN is low. The track-and-hold amplifier goes into the
hold mode on the falling edge of CS. In this mode, the BUSY
/INT pin assumes its BUSY function. BUSY goes low at the start
of conversion, stays low during the conversion and returns high
when the conversion is complete. It is normally used in parallel
interfaces to drive the microprocessor into a WAIT state for the
duration of conversion. Mode 2 is not relevant for the AD7870A
device.
Figure 16 shows the Mode 2 timing diagram for the 12-bit
parallel data output format (12/8/CLK = +5 V). In this case, the
ADC behaves like slow memory. The major advantage of this
interface is that it allows the microprocessor to start conversion,
WAIT and then read data with a single READ instruction. The
user does not have to worry about servicing interrupts or
ensuring that software delays are long enough to avoid reading
during conversion.
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