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參數(shù)資料
| 型號： | AD7888ARUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/17頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CH SRL 16-TSSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 3.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
AD7888
–5–
PIN CONFIGURATIONS
SOIC AND TSSOP
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
CS
REF IN/REF OUT
VDD
AGND
AIN1
AIN2
AIN3
AIN4
SCLK
DOUT
DIN
AGND
AIN8
AIN7
AIN6
AIN5
AD7888
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7888 and also frames the serial data transfer.
2
REF IN/REF OUT
Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888.
Alternatively, the internal reference can be disabled and an external reference applied to this input.
The voltage range for the external reference is from 1.2 V to VDD.
3VDD
Power Supply Input. The VDD range for the AD7888 is from 2.7 V to 5.25 V.
4, 13
AGND
Analog Ground. Ground reference point for all circuitry on the AD7888. All analog input signals and
any external reference signals should be referred to this AGND voltage. Both of these pins should
connect to the AGND plane of a system.
5–12
AIN1–AIN8
Analog Input 1 through Analog Input 8. Eight single-ended analog input channels that are multiplexed
into the on-chip track/hold. The analog input channel to be converted is selected by using the ADD0
through ADD2 bits of the Control Register. The input range for all input channels is 0 to VREF. Any
unused input channels should be connected to AGND to avoid noise pickup.
14
DIN
Data In. Logic Input. Data to be written to the AD7888’s Control Register is provided on this input
and is clocked into the register on the rising edge of SCLK (see Control Register section).
15
DOUT
Data Out. Logic Output. The conversion result from the AD7888 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists
of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first.
16
SCLK
Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing
serial data to the Control Register. This clock input is also used as the clock source for the AD7888’s
conversion process.
REV. C
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