參數(shù)資料
型號(hào): AD7889-1ACBZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 32/41頁
文件大?。?/td> 0K
描述: IC ADC 12BIT CTRLR TOUCH 12WLCSP
產(chǎn)品變化通告: 8mm Carrier Tape Changes 28/Feb/2012
標(biāo)準(zhǔn)包裝: 3,000
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
數(shù)據(jù)接口: I²C,串行
數(shù)據(jù)速率/采樣率 (SPS,BPS): 105k
電壓基準(zhǔn): 外部
電源電壓: 1.6 V ~ 3.6 V
電流 - 電源: 10nA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-UFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 12-WLCSP
包裝: 帶卷 (TR)
AD7879/AD7889
Rev. C | Page 37 of 40
GROUNDING AND LAYOUT
For detailed information on grounding and layout considerations
for the AD7879/AD7889, refer to the AN-577 Application Note,
Layout and Grounding Recommendations for Touch Screen
Digitizers.
LEAD FRAME CHIP SCALE PACKAGES
The lands on the lead frame chip scale package (CP-16-10) are
rectangular. The printed circuit board (PCB) pad for these lands
should be 0.1 mm longer than the package land length and
0.05 mm wider than the package land width. Center the land on
the pad to maximize the solder joint size.
The bottom of the lead frame chip scale package has a central
thermal pad. The thermal pad on the PCB should be at least as
large as this exposed pad. To avoid shorting, provide a clearance
of at least 0.25 mm between the thermal pad and the inner
edges of the land pattern on the PCB. Thermal vias can be used
on the PCB thermal pad to improve the thermal performance of
the package. If vias are used, incorporate them into the thermal
pad at a 1.2 mm pitch grid. The via diameter should be between
0.3 mm and 0.33 mm, and the via barrel should be plated with
1 oz. of copper to plug the via.
Connect the PCB thermal pad to GND.
WLCSP ASSEMBLY CONSIDERATIONS
For detailed information on the WLCSP PCB assembly and
reliability, see the AN-617 Application Note, MicroCSP Wafer
Level Chip Scale Package.
NC = NO CONNECT
1
Y+
2
NC
3
NC
4
X–
11
NC
12
10
NC
9
DOUT
5
6
7
8
15
16
14
13
07667-
045
AD7879/
AD7889
PENIRQ/INT/DAV
Y–
DI
N
G
ND
SCL
V
CC
/RE
F
X+
AUX
/
VBA
T/
GP
IO
CS
TOUCH
SCREEN
0.1F
0.1F TO 10F
(OPTIONAL)
VOLTAGE
REGULATOR
MAIN
BATTERY
INT
SCLK
MISO
MOSI
SPI
IN
TE
R
F
ACE
HOST
CS
Figure 46. Typical Application Circuit
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