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參數(shù)資料
| 型號(hào)： | AD7890BRZ-4REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 8CH 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 117k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
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AD7890
Rev. C | Page 14 of 28
When using the device in the external-clocking mode, the
output register can be read at any time and the most up-to-date
conversion result is obtained. However, reading data from the
output register or writing data to the control register during
conversion or during the 500 ns prior to the next CONVST
results in reduced performance from the part. A read operation
to the output register has the most effect on performance with
the signal-to-noise ratio likely to degrade, especially when
higher serial clock rates are used while the code flicker from the
part also increases (see the Performance section).
Figure 7 shows the timing and control sequence required to
obtain optimum performance from the part in the external
clocking mode. In the sequence shown, conversion is initiated
on the rising edge of CONVST and new data is available in the
output register of the AD7890 5.9 μs later. Once the read
operation has taken place, a further 500 ns should be allowed
before the next rising edge of CONVST to optimize the settling
of the track/hold before the next conversion is initiated.
The diagram shows the read operation and the write operation
taking place in parallel. On the sixth falling edge of SCLK in the
write sequence the internal pulse is initiated. Assuming MUX OUT
is connected to SHA IN, 2 μs are required between this sixth
falling edge of SCLK and the rising edge of CONVST to allow
for the full acquisition time of the track/hold amplifier. With
the serial clock rate at its maximum of 10 MHz, the achievable
throughput rate for the part is 5.9 μs (conversion time) plus 0.6
μs (six serial clock pulses before internal pulse is initiated) plus
2 μs (acquisition time). This results in a minimum throughput
time of 8.5 μs (equivalent to a throughput rate of 117 kHz). If
the part is operated with a slower serial clock, it affects the
achievable throughput rate for optimum performance.
RFS
TFS
500ns MIN
CONVST
SCLK
NEXT CONVERSION
START COMMAND
CONVERSION IS
INITIATED AND
TRACK/HOLD GOES
INTO HOLD
CONVERSION
ENDS 5.9s
LATER
SERIAL READ
AND WRITE
OPERATIONS
READ AND WRITE
OPERATIONS SHOULD END
500ns PRIOR TO NEXT
RISING EDGE OF CONVST
tCONVERT
01
35
7-
00
7
Figure 7. External Clocking (Slave) Mode Timing Sequence for Optimum Performance
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