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| 型號： | AD7890BRZ-4REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 8CH 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 117k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
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AD7890
Rev. C | Page 16 of 28
CEXT FUNCTIONING
The CEXT input on the AD7890 provides a means of determining
how long after a new channel address is written to the part that
a conversion can take place. The reason behind this is two-fold.
First, when the input channel to the AD7890 is changed, the
input voltage on this new channel is likely to be very different
from the previous channel voltage. Therefore, the part’s track/
hold has to acquire the new voltage before an accurate
conversion can take place. An internal pulse delays any
conversion start command (as well as the signal to send the
track/hold into hold) until after this pulse has timed out.
The second reason is to allow the user to connect external
antialiasing or signal conditioning circuitry between the
MUX OUT pin and the SHA IN pin. This external circuitry
introduces extra settling time into the system. The CEXT pin
provides a means for the user to extend the internal pulse to
take this extra settling time into account. Effectively varying the
value of the capacitor on the CEXT pin varies the duration of the
internal pulse. Figure 9 shows the relationship between the
value of the CEXT capacitor and the internal delay.
64
56
48
40
32
24
16
8
0
250
500
750
1000
1250
1500
1750
2000
01
35
7-
00
9
IN
T
E
RN
AL
P
U
L
S
E
W
IDT
H
(
s)
CEXT CAPACITANCE (pF)
TA = +85°C
TA = –40°C
TA = +25°C
Figure 9. Internal Pulse Width vs. CEXT
The duration of the internal pulse can be seen on the CEXT pin.
The CEXT pin goes from a low to a high when a serial write to
the part is initiated (on the falling edge of TFS). It starts to
discharge on the sixth falling edge of SCLK in the serial write
operation. Once the CEXT pin has discharged to crossing its
nominal trigger point of 2.5 V, the internal pulse is timed out.
The internal pulse is initiated each time a write operation to the
control register takes place. As a result, the pulse is initiated and
the conversion process delayed for all software conversion start
commands. For hardware conversion start, it is possible to
separate the conversion start command from the internal pulse.
If the multiplexer output (MUX OUT) is connected directly to
the track/hold input (SHA IN), then no external settling has to
be taken into account by the internal pulse width. In applications
where the multiplexer is switched and conversion is not
initiated until more than 2 μs after the channel is changed (as is
possible with a hardware conversion start), the user does not
have to worry about connecting any capacitance to the
CEXT pin. The 2 μs equates to the track/hold acquisition time of
the AD7890. In applications where the multiplexer is switched
and conversion is initiated at the same time (such as with a
software conversion start), a 120 pF capacitor should be
connected to CEXT to allow for the acquisition time of the
track/hold before conversion is initiated.
If external circuitry is connected between the MUX OUT pin
and SHA IN pin, then the extra settling time introduced by this
circuitry must be taken into account. In the case where the
multiplexer change command and the conversion start
command are separated, they need to be separated by greater
than the acquisition time of the AD7890 plus the settling time
of the external circuitry if the user does not have to worry about
the CEXT capacitance. In applications where the multiplexer is
switched and conversion is initiated at the same time (such as
with a software conversion start), the capacitor on CEXT needs to
allow for the acquisition time of the track/hold and the settling
time of the external circuitry before conversion is initiated.
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