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參數(shù)資料
| 型號： | AD7924BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 411K |
| 代理商： | AD7924BRU |
AD7904/AD7914/AD7924
–13–
REV. 0
Table I. Control Register Bit Functions
MSB
WRITE
LSB
CODING
SEQ1 DONTC
DONTC
ADD1 ADD0
PM1
PM0
SEQ0
DONTC
RANGE
Bit
Mnemonic
Comment
11
WRITE
The value written to this bit of the Control Register determines whether the following 11 bits will be loaded
to the control register or not. If this bit is a 1 then the following 11 bits will be written to the control register; if it
is a 0 then the remaining 11 bits are not loaded to the control register and so it remains unchanged.
The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the use of the
sequencer function. (See Table IV.)
10
SEQ1
9–8
7–6
DONTCARE
ADD1, ADD0 These two address bits are loaded at the end of the present conversion sequence and select which analog
input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive
sequence as described in Table IV. The selected input channel is decoded as shown in Table II. The
address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data,
see the Serial Interface section. The next channel to be converted on will be selected by the mux on the
fourteenth SCLK falling edge.
PM1, PM0
Power Management Bits. These two bits decode the mode of operation of the AD7904/AD7914/AD7924
as shown in Table III.
SEQ0
The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the use of the
sequencer function. (See Table IV.)
DONTCARE
RANGE
This bit selects the analog input range to be used on the AD7904/AD7914/AD7924. If it is set to 0 then the
analog input range will extend from 0 V to 2
×
REF
IN
. If it is set to 1 then the analog input range will extend
from 0 V to REF
IN
(for the next conversion). For 0 V to 2
×
REF
IN
, V
DD
= 4.75 V to 5.25 V.
CODING
This bit selects the type of output coding the AD7904/AD7914/AD7924 will use for the conversion result.
If this bit is set to 0 the output coding for the part will be twos complement. If this bit is set to 1 then the
output coding from the part will be straight binary (for the next conversion).
5, 4
3
2
1
0
CODE
1.0
0
4096
I
0
–0.4
–0.8
–1.0
0.2
–0.2
–0.6
2048
0.6
V
= V
= 5V
TEMP = 25 C
0.4
0.8
2560
3072
3584
512
1024
1536
TPC 6. AD7924 Typical INL
CONTROL REGISTER
The Control Register on the AD7904/AD7914/AD7924 is a 12-bit, write-only register. Data is loaded from the DIN pin of the
AD7904/AD7914/AD7924 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conver-
sion result is read from the part. The data transferred on the DIN line corresponds to the AD7904/AD7914/AD7924 configuration
for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling
clock edges (after
CS
falling edge) is loaded to the Control Register. MSB denotes the first bit in the data stream. The bit functions
are outlined in Table I.
CODE
1.0
0
4096
D
0
–0.4
–0.8
–1.0
0.2
–0.2
–0.6
2048
0.6
0.4
0.8
2560
3072
3584
512
1024
1536
V
= V
= 5V
TEMP = 25 C
TPC 7. AD7924 Typical DNL
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