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參數(shù)資料
| 型號： | AD7924BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 411K |
| 代理商： | AD7924BRU |
AD7904/AD7914/AD7924
–23–
REV. 0
instructions. This situation will result in nonequidistant sam-
pling as the transmit instruction is occurring on a SCLK edge. If
the number of SCLKs between interrupts is a whole integer figure
of N, then equidistant sampling will be implemented by the DSP.
AD7904/
AD7914/
AD7924
*
ADSP-218x
*
SCLK
DR
RFS
TFS
DT
V
DD
SCLK
DOUT
CS
DIN
V
DRIVE
*
ADDITIONAL PINS REMOVED FOR CLARITY
Figure 20. Interfacing to the ADSP-218x
AD7904/AD7914/AD7924 to DSP563xx
The connection diagram in Figure 21 shows how the
AD7904/AD7914/AD7924 can be connected to the ESSI
(Synchronous Serial Interface) of the DSP563xx family of DSPs
from Motorola. Each ESSI (two on board) is operated in
Synchronous Mode (SYN bit in CRB = 1) with internally
generated 1-bit clock period frame sync for both Tx and Rx (bits
FSL1 = 0 and FSL0 = 0 in CRB). Normal operation of the ESSI
is selected by making MOD = 0 in the CRB. Set the word length
to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. The FSP bit
in the CRB should
be set to 1 so the frame sync is negative. It
should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the DSP563xx
provides equidistant sampling.
In the example shown in Figure 21 below, the serial clock is
taken from the ESSI so the SCK0 pin must be set as an output,
SCKD = 1. The V
DRIVE
pin of the AD7904/AD7914/AD7924
takes the same supply voltage as that of the DSP563xx. This
allows the ADC to operate at a higher voltage than the serial
interface, i.e., DSP563xx, if necessary.
AD7904/
AD7914/
AD7924
*
DSP563xx
*
SCK
SRD
STD
SC2
V
DD
SCLK
DOUT
CS
DIN
V
*
ADDITIONAL PINS REMOVED FOR CLARITY
Figure 21. Interfacing to the DSP563xx
APPLICATION HINTS
Grounding and Layout
The AD7904/AD7914/AD7924 have very good immunity to
noise on the power supplies as can be seen by the PSRR vs.
Supply Ripple Frequency plot, TPC 3. However, care should
still be taken with regard to grounding and layout.
The printed circuit board that houses the AD7904/AD7914/
AD7924 should be designed such that the analog and digital
sections are separated and confined to certain areas of the
board. This facilitates the use of ground planes that can be
separated easily. A minimum etch technique is generally best
for ground planes as it gives the best shielding. All three
AGND pins of the AD7904/AD7914/AD7924 should be sunk
in the AGND plane. Digital and analog ground planes should
be joined at only one place. If the AD7904/AD7914/AD7924
is in a system where multiple devices require an AGND to
DGND connection, the connection should still be made at
one point only, a star ground point that should be established
as close as possible to the AD7904/AD7914/AD7924.
Avoid running digital lines under the device as these will
couple noise onto the die. The analog ground plane should
be allowed to run under the AD7904/AD7914/AD7924 to
avoid noise coupling. The power supply lines to the AD7904/
AD7914/AD7924 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals, like clocks,
should be shielded with digital ground to avoid radiating
noise to other sections of the board, and clock signals should
never be run near the analog inputs. Avoid crossover of digi-
tal and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique is
by far the best but is not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground planes while signals are placed on the
solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10
μ
F tantalum in parallel with 0.1
μ
F
capacitors to AGND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device, ideally right up against the device. The 0.1
μ
F capacitors
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), such as the common ceramic types or
surface mount types, which provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
Evaluating the AD7904/AD7914/AD7924 Performance
The recommended layout for the AD7904/AD7914/AD7924 is
outlined in the evaluation board for the AD7904/AD7914/AD7924.
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from the PC via the EVAL-BOARD
CONTROLLER. The EVAL-BOARD CONTROLLER can be
used in conjunction with the AD7904/AD7914/AD7924
evaluation board, as well as many other Analog Devices evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the AD7904/AD7914/AD7924.
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7904/AD7914/
AD7924. The software and documentation are on a CD shipped
with the evaluation board.
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