參數(shù)資料
型號: AD7945BRS-REEL
廠商: Analog Devices Inc
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC DAC 12BIT MULT PARALL 20-SSOP
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1,500
設置時間: 600ns
位數(shù): 12
數(shù)據接口: 并聯(lián)
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 25µW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 20-SSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 1.7M
AD7943/AD7945/AD7948
REV. B
–8–
TERMINOLOGY
Relative Accuracy
Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally
expressed in Least Significant Bits or as a percentage of full-
scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Gain Error
Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s
in the DAC after offset error has been adjusted out and is ex-
pressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Output Leakage Current
Output leakage current is current which flows in the DAC lad-
der switches when these are turned off. For the IOUT1 terminal,
it can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s.
Output Capacitance
This is the capacitance from the IOUT1 pin to AGND.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified both with the AD843 as the output op amp in the
normal current mode and with the AD820 in the biased current
mode.
Digital to Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-s. It is measured with the reference input connected
to AGND and the digital inputs toggled between all 1s and all
0s. As with Settling Time, it is specified with both the AD817
and the AD820.
AC Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded in the DAC.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the IOUT1 pin and subsequently on
the op amp output. This noise is digital feedthrough.
PIN CONFIGURATIONS
DIP/SOP
SSOP
DIP/SOP/SSOP
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
TOP VIEW
(Not to Scale)
AD7945
DB5
DB6
DB7
AGND
DGND
DB11
DB8
DB9
DB10
DB4
DB3
DB2
VREF
VDD
WR
DB1
DB0
CS
IOUT1
RFB
TOP VIEW
(Not to Scale)
AD7943
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IOUT1
IOUT2
AGND
STB1
LD1
SRO
SRI
STB2
RFB
VREF
VDD
CLR
DGND
STB4
STB3
LD2
TOP VIEW
(Not to Scale)
AD7943
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
NC = NO CONNECT
STB2
SRI
SRO
IOUT2
AGND
STB1
LD1
NC
LD2
STB3
STB4
VREF
VDD
CLR
DGND
NC
IOUT1
RFB
TOP VIEW
(Not to Scale)
AD7948
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DB4
DB5
DB6
AGND
DGND
CSMSB
DB7 (MSB)
CTRL
DF/
DOR
DB3
DB2
DB1
VREF
VDD
WR
DB0 (LSB)
LDAC
CSLSB
IOUT1
RFB
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