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參數(shù)資料
| 型號： | AD7945BRS-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT MULT PARALL 20-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時間： | 600ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 25µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 1.7M |
AD7943/AD7945/AD7948
REV. B
–14–
BIPOLAR OPERATION
(Four-Quadrant Multiplication)
Figure 15 shows the standard connection diagram for bipolar
operation of the AD7943, AD7945 and AD7948. The coding is
offset binary as shown in Table IV. When VIN is an ac signal,
the circuit performs four-quadrant multiplication. Resistors R1
and R2 are for gain error adjustment and are not needed in
many applications where the device gain error specifications are
adequate. To maintain the gain error specifications, resistors
R3, R4 and R5 should be ratio matched to 0.01%.
IOUT1
IOUT2
A1
VOUT
SIGNAL GROUND
AGND
DAC
VREF
R1 20
AD7943/45/48
VIN
R2 10
RFB
C1
R4 20k
A2
10k
20k
R3
R5
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLAIRITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5 – 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 15. Bipolar Operation (Four-Quadrant
Multiplication)
Suitable dual amplifiers for use with Figure 15 are the OP270
(low noise, low bandwidth, 15 kHz), the AD712 (medium
bandwidth, 200 kHz) or the AD827 (wide bandwidth, 1 MHz).
Table IV. Bipolar (Offset Binary) Code
Table Digital Input
Analog Output
MSB
LSB
(VOUT as Shown in Figure 15)
1111 1111 1111
+VREF (2047/2048)
1000 0000 0001
+VREF (1/2048)
1000 0000 0000
+VREF (0/2048) = 0
0111 1111 1111
–VREF (1/2048)
0000 0000 0001
–VREF (2047/2048)
0000 0000 0000
–VREF (2048/2048) = –VREF
NOTE
Nominal LSB size for the circuit of Figure 15 is given by: V REF (1/2048).
SINGLE SUPPLY APPLICATIONS
The “-B” versions of the devices are specified and tested for
single supply applications. Figure 16 shows the recommended
circuit for operation with a single +5 V to +3.3 V supply. The
IOUT2 and AGND terminals are biased to 1.23 V. Thus, with 0 V
applied to the VREF terminal, the output will go from 1.23 V (all
0s loaded to the DAC) to 2.46 V (all 1s loaded). With 2.45 V
applied to the VREF terminal, the output will go from 1.23 V (all
0s loaded) to 0.01 V (all 1s loaded). It is important when con-
sidering INL in a single-supply system to realize that most
single-supply amplifiers cannot sink current and maintain zero
volts at the output. In Figure 16, with VREF = 2.45 V the re-
quired sink current is 200
A. The minimum output voltage
level is 10 mV. Op amps like the OP295 are capable of main-
taining this level while sinking 200
A.
Figure 16 shows the IOUT2 and AGND terminals being driven
by an amplifier. This is to maintain the bias voltage at 1.23 V
as the impedance seen looking into the IOUT2 terminal changes.
This impedance is code dependent and varies from infinity (all
0s loaded in the DAC) to about 6 k
minimum. The AD589
has a typical output resistance of 0.6
and it can be used to
drive the terminals directly. However, this will cause a typical
linearity degradation of 0.2 LSBs. If this is unacceptable then
the buffer amplifier is necessary. Figure 9 shows the typical
linearity performance of the AD7943/AD7945/AD7948 when
used as in Figure 16 with VDD set at +3.3 V and VREF = 0 V.
IOUT1
IOUT2
A1
VOUT
SIGNAL GROUND
A1: OP295
AD822
OP283
AGND
DAC
VREF
AD7943/45/48
VIN
RFB
C1
A1
+5V
5.6k
AD589
+3.3V
VDD
DGND
Figure 16. Single Supply System
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