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參數(shù)資料
| 型號(hào)： | AD7982BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 1MSPS PULSR 10LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Motor Control |
| 設(shè)計(jì)資源： | Converting a Single-Ended Signal with AD7982 Differential PulSAR ADC (CN0032) Precision Single-Supply Differential ADC Driver for Industrial-Level Signals (CN0180) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 8.6mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
| 產(chǎn)品目錄頁(yè)面： | 780 (CN2011-ZH PDF) |
| 其它名稱： | AD7982BCPZ-RL7DKR |
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Data Sheet
AD7982
Rev. B | Page 19 of 24
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7982s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7982s is shown in
Figure 33, and the corresponding timing is given in Figure 34.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7982 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided it has an acceptable hold time.
After the 18th SCK falling edge or when SDI goes high (whichever
occurs first), SDO returns to high impedance and another
AD7982 can be read.
AD7982
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
06513-
020
CS1
CS2
AD7982
SDI
SDO
CNV
SCK
Figure 33. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO
D17
D16
D15
D1
D0
tDIS
SCK
1
2
3
34
35
36
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
16
17
tSCK
tSCKL
tSCKH
D0
D17
D16
19
20
18
SDI(CS2)
06513-
021
Figure 34. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
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