參數(shù)資料
型號(hào): AD7982BCPZ-RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 18BIT 1MSPS PULSR 10LFCSP
產(chǎn)品培訓(xùn)模塊: Motor Control
設(shè)計(jì)資源: Converting a Single-Ended Signal with AD7982 Differential PulSAR ADC (CN0032)
Precision Single-Supply Differential ADC Driver for Industrial-Level Signals (CN0180)
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
位數(shù): 18
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 8.6mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 1 個(gè)差分,單極
產(chǎn)品目錄頁(yè)面: 780 (CN2011-ZH PDF)
其它名稱: AD7982BCPZ-RL7DKR
Data Sheet
AD7982
Rev. B | Page 21 of 24
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7982s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7982s is shown in
Figure 37, and the corresponding timing is given in Figure 38.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7982 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7982s in the chain, provided the
digital host has an acceptable hold time. The maximum conversion
rate may be reduced due to the total readback time.
CONVERT
DATA IN
CLK
DIGITAL HOST
06513-
024
AD7982
SDI
SDO
CNV
B
SCK
AD7982
SDI
SDO
CNV
A
SCK
Figure 37. Chain Mode Without Busy Indicator Connection Diagram
SDOA = SDIB
DA17
DA16
DA15
SCK
1
2
3
34
35
36
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
16
17
tSCK
tSCKL
tSCKH
DA0
19
20
18
SDIA = 0
SDOB
DB17
DB16
DB15
DA1
DB1
DB0
DA17
DA16
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
06513-
025
Figure 38. Chain Mode Without Busy Indicator Serial Interface Timing
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