Data Sheet
AD7982
Rev. B | Page 5 of 24
TIMING SPECIFICATIONS
TA = 40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.1 Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
500
710
ns
Acquisition Time
tACQ
290
ns
Time Between Conversions
tCYC
1000
ns
CNV Pulse Width (CS Mode)
tCNVH
10
ns
SCK Period (CS Mode)
tSCK
VIO Above 4.5 V
10.5
ns
VIO Above 3 V
12
ns
VIO Above 2.7 V
13
ns
VIO Above 2.3 V
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
11.5
ns
VIO Above 3 V
13
ns
VIO Above 2.7 V
14
ns
VIO Above 2.3 V
16
ns
SCK Low Time
tSCKL
4.5
ns
SCK High Time
tSCKH
4.5
ns
SCK Falling Edge to Data Remains Valid
tHSDO
3
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 4.5 V
9.5
ns
VIO Above 3 V
11
ns
VIO Above 2.7 V
12
ns
VIO Above 2.3 V
14
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
tEN
VIO Above 3 V
10
ns
VIO Above 2.3 V
15
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
20
ns
SDI Valid Setup Time from CNV Rising Edge
tSSDICNV
5
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
2
ns
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
2
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
3
ns
SDI High to SDO High (Chain Mode with Busy Indicator)
tDSDOSDI
15
ns
500A
IOL
500A
IOH
1.4V
TO SDO
CL
20pF
06
51
3-
00
2
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
Y% VIO1
VIH2
VIL2
VIH2
tDELAY
1FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
06
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3-
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3
Figure 3. Voltage Levels for Timing