參數(shù)資料
型號(hào): AD7983BCPZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 7/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT 1.33MSPS 10LFCSP
標(biāo)準(zhǔn)包裝: 5,000
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 1.33M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 12mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 1 個(gè)差分,單極
AD7983
Rev. A | Page 15 of 24
VOLTAGE REFERENCE INPUT
The AD7983 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for example,
a reference buffer using the AD8031 or the AD8605, a ceramic
chip capacitor is appropriate for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference-decoupling capacitor value as small as
2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
POWER SUPPLY
The AD7983 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.0 V. To reduce the
number of supplies needed, VIO and VDD can be tied together.
The AD7983 is independent of power supply sequencing between
VIO and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 25.
80
55
1
1000
FREQUENCY (kHz)
P
S
RR
(
d
B)
10
100
75
70
65
60
06
97
4-
01
0
Figure 25. PSRR vs. Frequency
To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V (±5%).
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