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參數(shù)資料
| 型號： | AD7984BRMZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT 1.3MSPS SAR 10MSOP |
| 設計資源： | Converting a Single-Ended Signal with AD7984 Differential PulSAR ADC (CN0033) |
| 標準包裝： | 1,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 1.33M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 14mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
AD7984
Rev. A | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7984
TOP VIEW
(Not to Scale)
06
97
3-
00
4
Figure 4. 10-Lead MSOP Pin Configuration
REF
VDD
IN+
IN–
GND
VIO
SDI
SCK
SDO
CNV
06973-005
1
2
3
4
10
9
8
7
5
6
*EXPOSED PADDLE CAN BE CONNECTED
TO GROUND.
AD7984
(EXPOSED
PAD)*
Figure 5. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The REF range is 2.9 V to 5.1 V. This pin is referred to the GND pin and
should be decoupled closely to the GND pin with a 10 μF capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Differential Positive Analog Input.
4
IN
AI
Differential Negative Analog Input.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its rising edge, it initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data should be read when CNV is high.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The
digital data level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low. If SDI or CNV is low when the conversion is complete,
the busy indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, 3 V, or 5 V).
1 AI = analog input, DI = digital input, DO = digital output, and P = power.
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相關代理商/技術參數(shù) |
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