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參數(shù)資料
| 型號(hào)： | AD7986BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT 2MSPS SAR 20LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Motor Control |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 34mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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AD7986
Rev. B | Page 16 of 28
VOLTAGE REFERENCE INPUT
The AD7986 allows the choice of a very low temperature drift
internal voltage reference, an external reference, or an external
buffered reference.
The internal reference of the AD7986 provides excellent
performance and can be used in almost all applications.
Internal Reference, REF = 4.096V (PDREF = Low)
To use the internal reference, the PDREF input must be low.
This enables the on-chip band gap reference and buffer, result-
ing in a 4.096 V reference on the REF pin (1.2 V on REFIN).
The internal reference is temperature compensated to 4.096 V ±
15 mV. The reference is trimmed to provide a typical drift of
10 ppm/°C.
The output resistance of REFIN is 6 k when the internal
reference is enabled. It is necessary to decouple this pin with a
ceramic capacitor of at least 100 nF. The output resistance of
REFIN and the decoupling capacitor form an RC filter, which
helps to reduce noise.
Because the output impedance of REFIN is typically 6 k, relative
humidity (among other industrial contaminants) can directly
affect the drift characteristics of the reference. A guard ring is
typically used to reduce the effects of drift under such circum-
stances. However, the fine pitch of the AD7986 makes this
difficult to implement. One solution, in these industrial and
other types of applications, is to use a conformal coating, such as
Dow Corning 1-2577 or HumiSeal 1B73.
External 1.2 V Reference and Internal Buffer (PDREF = High)
To use an external reference along with the internal buffer, PDREF
should be high. This powers down the internal reference and
allows the 1.2 V reference to be applied to REFIN, producing
4.096 V (typically) on the REF pin.
External Reference (PDREF = High, REFIN = Low)
To apply an external reference voltage directly to the REF pin,
PDREF should be tied high, and REFIN should be tied low.
BVDD should also be driven to the same potential as REF. For
example, if REF = 2.5 V, BVDD should be tied to 2.5 V.
The advantages of directly using the external voltage reference are:
The SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a larger reference voltage (5 V)
instead of a typical 4.096 V reference when the internal
reference is used. This is calculated by
=
0
.
5
096
.
4
log
20
SNR
The power savings when the internal reference is powered
down (PDREF high).
Reference Decoupling
The AD7986 voltage reference input, REF, has a dynamic input
impedance that requires careful decoupling between the REF
and REFGND pins. The Layout section describes how this can
be done.
When using an external reference, a very low impedance source
(for example, a reference buffer using the AD8031 or the
AD8605), and a 10 F (X5R, 0805 size) ceramic chip capacitor
are appropriate for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 F (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference decoupling capacitor with values as small
as 2.2 F can be used with minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and REFGND pins.
POWER SUPPLY
The AD7986 uses four power supply pins: an analog supply
(AVDD), a buffer supply (BVDD), a digital supply (DVDD),
and a digital input/output interface supply (VIO). VIO allows
direct interface with any logic between 1.8 V and 2.7 V. To reduce
the number of supplies needed, VIO, DVDD, and AVDD can
be tied together. The AD7986 is independent of power supply
sequencing among all of its supplies. Additionally, it is very
insensitive to power supply variations over a wide frequency range.
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