參數(shù)資料
型號: AD7986BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 16/28頁
文件大小: 0K
描述: IC ADC 18BIT 2MSPS SAR 20LFCSP
產(chǎn)品培訓(xùn)模塊: Motor Control
標(biāo)準(zhǔn)包裝: 1
位數(shù): 18
采樣率(每秒): 2M
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 34mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 20-LFCSP-VQ
包裝: 托盤
輸入數(shù)目和類型: 1 個(gè)差分,雙極
產(chǎn)品目錄頁面: 780 (CN2011-ZH PDF)
AD7986
Rev. B | Page 23 of 28
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7986 devices
on a 3-wire serial interface. It is only available in normal conver-
sion mode (TURBO = low). This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7986 devices is
shown in Figure 33, and the corresponding timing is given in
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO, and the AD7986 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7986 devices in the chain,
provided that the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7986
SDI
SDO
CNV
B
SCK
AD7986
SDI
SDO
CNV
A
SCK
TURBO
07956-
026
Figure 33. Chain Mode Without Busy Indicator Connection Diagram
SDOA = SDIB
DA17 DA16 DA15
SCK
1
2
3
39
53
54
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
4
17
tSCK
tSCKH
tSCKL
DA0
19
38
18
SDOB = SDIC
DB17 DB16 DB15
DA1
DB1
DB0 DA17 DA16
55
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC17 DC16 DC15
DA1
DA0
DC1
DC0
DA16
21
35
36
20
37
DB1
DB0 DA17
DB17 DB16
tDSDOSDI
tHSCKCNV
DA0
tDSDOSDI
07956-
027
TURBO= 0
tSSCKCNV
Figure 34. Chain Mode Without Busy Indicator Serial Interface Timing
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