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參數(shù)資料
| 型號： | AD800-52BRZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK\DATA RECOVERY PLL 20SOIC |
| 標準包裝： | 1,000 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），扇出緩沖器（分配） |
| PLL： | 是 |
| 主要目的： | DS-3，STS-1 |
| 輸入： | ECL |
| 輸出： | ECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 51.84MHz |
| 電源電壓： | -4.5 V ~ -5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
FUNCTIONAL BLOCK DIAGRAM
VCO
DATA
INPUT
AD800/AD802
CD
RETIMED
DATA
OUTPUT
FRAC
OUTPUT
LOOP
FILTER
DET
fDET
∑
COMPENSATING
ZERO
RECOVERED
CLOCK
OUTPUT
RETIMING
DEVICE
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Clock Recovery and Data Retiming
Phase-Locked Loop
AD800/AD802
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
PRODUCT DESCRIPTION
The AD800 and AD802 employ a second order phase-locked
loop architecture to perform clock recovery and data retiming
on Non-Return to Zero, NRZ, data. This architecture is
capable of supporting data rates between 20 Mbps and 160
Mbps. The products described here have been defined to work
with standard telecommunications bit rates. 45 Mbps DS-3 and
52 Mbps STS-1 are supported by the AD800-45 and
AD800-52 respectively. 155 Mbps STS-3 or STM-1 are
supported by the AD802-155.
Unlike other PLL-based clock recovery circuits, these devices
do not require a preamble or an external VCXO to lock onto
input data. The circuit acquires frequency and phase lock using
two control loops. The frequency acquisition control loop
initially acquires the clock frequency of the input data. The
phase-lock loop then acquires the phase of the input data, and
ensures that the phase of the output signals track changes in the
phase of the input data. The loop damping of the circuit is
dependent on the value of a user selected capacitor; this defines
jitter peaking performance and impacts acquisition time. The
devices exhibit 0.08 dB jitter peaking, and acquire lock on
random or scrambled data within 4
× 105 bit periods when
using a damping factor of 5.
FEATURES
Standard Products
44.736 Mbps—DS-3
51.84 Mbps—STS-1
155.52 Mbps—STS-3 or STM-1
Accepts NRZ Data, No Preamble Required
Recovered Clock and Retimed Data Outputs
Phase-Locked Loop Type Clock Recovery—No Crystal
Required
Random Jitter: 20 Peak-to-Peak
Pattern Jitter: Virtually Eliminated
10KH ECL Compatible
Single Supply Operation: –5.2 V or +5 V
Wide Operating Temperature Range: –40 C to +85 C
During the process of acquisition the frequency detector
provides a Frequency Acquisition (FRAC) signal which
indicates that the device has not yet locked onto the input data.
This signal is a series of pulses which occur at the points of cycle
slip between the input data and the synthesized clock signal.
Once the circuit has acquired frequency lock no pulses occur at
the FRAC output.
The inclusion of a precisely trimmed VCO in the device
eliminates the need for external components for setting center
frequency, and the need for trimming of those components. The
VCO provides a clock output within
±20% of the device center
frequency in the absence of input data.
The AD800 and AD802 exhibit virtually no pattern jitter, due
to the performance of the patented phase detector. Total loop
jitter is 20
° peak-to-peak. Jitter bandwidth is dictated by mask
programmable fractional loop bandwidth. The AD800, used for
data rates < 90 Mbps, has been designed with a nominal loop
bandwidth of 0.1% of the center frequency. The AD802, used
for data rates in excess of 90 Mbps, has a loop bandwidth of
0.08% of center frequency.
All of the devices operate with a single +5 V or –5.2 V supply.
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