參數(shù)資料
型號(hào)： AD8000YRDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/21頁(yè)
文件大小： 0K
描述： IC OPAMP CF LN 100MA 8SOIC
產(chǎn)品培訓(xùn)模塊： Practical Guide High Speed PCB Layout
標(biāo)準(zhǔn)包裝： 98
放大器類型： 電流反饋
電路數(shù)： 1
轉(zhuǎn)換速率： 4100 V/µs
-3db帶寬： 1.58GHz
電流 - 輸入偏壓： 5µA
電壓 - 輸入偏移： 1000µV
電流 - 電源： 13.5mA
電流 - 輸出 / 通道： 100mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 12 V，±2.25 V ~ 6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm Width）裸露焊盤
供應(yīng)商設(shè)備封裝： 8-SOIC-EP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 769 (CN2011-ZH PDF)
Data Sheet
AD8000
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
12.6 V
Power Dissipation
Common-Mode Input Voltage
VS 0.7 V to +VS + 0.7 V
Differential Input Voltage
±VS
Storage Temperature
65°C to +125°C
Operating Temperature Range
40°C to +125°C
Lead Temperature Range
(Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is speci-
fied for device soldered in the circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
SOIC-8
80
30
°C/W
3 mm × 3 mm LFCSP
93
35
°C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8000 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric perfor-
mance of the AD8000. Exceeding a junction temperature of
175°C for an extended period of time can result in changes
in silicon devices, potentially causing degradation or loss of
functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the AD8000 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
PD = Quiescent Power + (Total Drive Power – Load Power)
(
)
L
2
OUT
L
OUT
S
D
R
V
–
R
V
2
V
I
V
P
×
+
×
=
RMS output voltages should be considered. If RL is referenced
to VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider
the worst case, when VOUT = VS/4 for RL to midsupply.
(
) (
)
L
S
D
R
/
V
I
V
P
2
4
+
×
=
In single-supply operation with RL referenced to VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
SOIC (80°C/W) and the LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
0
0.5
1.0
1.5
2.0
2.5
3.0
MAXIMUM
POWER
DISSIPATION
(W)
05321-063
–30 –20 –10
0
10
20
40
80
30
50
60
70
100
90
120
110
AMBIENT TEMPERATURE (
°C)
SOIC
LFCSP
–40
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
and loss of functionality.
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