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參數(shù)資料
型號(hào)： AD8021ARZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/29頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP VF LN LP LDIST 8SOIC
設(shè)計(jì)資源： Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
標(biāo)準(zhǔn)包裝： 1
放大器類型： 電壓反饋
電路數(shù)： 1
轉(zhuǎn)換速率： 460 V/µs
-3db帶寬： 560MHz
電流 - 輸入偏壓： 7.5µA
電壓 - 輸入偏移： 400µV
電流 - 電源： 7.8mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 24 V，±2.25 V ~ 12 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD8021ARZ-REEL7DKR
AD8021
Rev. F | Page 19 of 28
APPLICATIONS
The typical voltage feedback op amp is frequency stabilized
with a fixed internal capacitor, CINTERNAL, using dominant pole
compensation. To a first-order approximation, voltage feedback
op amps have a fixed gain bandwidth product. For example, if
its 3 dB bandwidth is 200 MHz for a gain of G = +1; at a gain
of G = +10, its bandwidth is only about 20 MHz. The AD8021 is
a voltage feedback op amp with a minimal CINTERNAL of about
1.5 pF. By adding an external compensation capacitor, CC, the
user can circumvent the fixed gain bandwidth limitation of
other voltage feedback op amps.
Unlike the typical op amp with fixed compensation, the
AD8021 allows the user to:
Maximize the amplifier bandwidth for closed-loop gains
between 1 and 10, avoiding the usual loss of bandwidth
and slew rate.
Optimize the trade-off between bandwidth and phase
margin for a particular application.
Match bandwidth in gain blocks with different noise gains,
such as when designing differential amplifiers (as shown in
FREQUENCY (Hz)
1M
OPEN-LOOP
GAIN
(dB)
100M
110
10k
10M
100
80
60
40
30
10
100k
90
70
50
20
1k
1G
10G
0
–10
180
135
45
90
0
PH
A
SE
(
D
egrees)
(B)
(C)
(A)
(C)
86
CC = 0pF
CC = 10pF
01888-058
(B)
Figure 58. Simplified Diagram of Open-Loop Gain and Phase Response
Figure 58 is the AD8021 gain and phase plot that has been
simplified for instructional purposes. Arrow A in Figure 58
shows a bandwidth of about 200 MHz and a phase margin at
about 60° when the desired closed-loop gain is G = +1 and
the value chosen for the external compensation capacitor is
CC = 10 pF. If the gain is changed to G = +10 and CC is fixed at
10 pF, then (as expected for a typical op amp) the bandwidth is
degraded to about 20 MHz and the phase margin increases to
90° (Arrow B). However, by reducing CC to 0 pF, the bandwidth
and phase margin return to about 200 MHz and 60° (Arrow C),
respectively. In addition, the slew rate is dramatically increased,
as it roughly varies with the inverse of CC.
1
2
3
4
5
6
7
8
9
10
0
NOISE GAIN (V/V)
12
3
4
5
6
7
8
9
10
11
01888-059
COMP
E
N
S
A
TION
CAP
ACITANCE
(pF)
Figure 59. Suggested Compensation Capacitance vs. Gain for
Maintaining 1 dB Peaking
Table 6 and Figure 59 provide recommended values of com-
pensation capacitance at various gains and the corresponding
slew rate, bandwidth, and noise. Note that the value of the
compensation capacitor depends on the circuit noise gain, not
the voltage gain. As shown in Figure 60, the noise gain, GN, of
an op amp gain block is equal to its noninverting voltage gain,
regardless of whether it is actually used for inverting or nonin-
verting gain. Thus,
Noninverting GN = RF/RG + 1
Inverting GN = RF/RG + 1
+
–
+
NONINVERTING
AD8021
3
2
5
6
1
RS
–VS
CCOMP
G = GN = +5
RF
1k
RG
249
AD8021
2
3
5
6
RF
1k
RG
249
–VS
CCOMP
G = –4
GN = +5
INVERTING
01
88
8-
0
60
Figure 60. The Noise Gain of Both is 5
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