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| 型號(hào)： | AD8034ARTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VF R-R DUAL LN SOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FastFET™ |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 80 V/µs |
| -3db帶寬： | 80MHz |
| 電流 - 輸入偏壓： | 1.5pA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 3.3mA |
| 電流 - 輸出 / 通道： | 60mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 24 V，±2.5 V ~ 12 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 769 (CN2011-ZH PDF) |
| 其它名稱： | AD8034ARTZ-REEL7DKR |
AD8033/AD8034
Rev. D | Page 16 of 24
THEORY OF OPERATION
The incorporation of JFET devices into the Analog Devices
high voltage XFCB process has enabled the ability to design the
AD8033/AD8034. The AD8033/AD8034 are voltage feedback
rail-to-rail output amplifiers with FET inputs and a bipolar-
enhanced common-mode input range. The use of JFET devices in
high speed amplifiers extends the application space into both the
low input bias current and low distortion, high bandwidth areas.
Using N-channel JFETs and a folded cascade input topology,
the common-mode input level operates from 0.2 V below the
negative rail to within 3.0 V of the positive rail. Cascading of
the input stage ensures low input bias current over the entire
common-mode range as well as CMRR and PSRR specifications
that are above 90 dB. Additionally, long-term settling issues that
normally occur with high supply voltages are minimized as a
result of the cascading.
OUTPUT STAGE DRIVE AND CAPACITIVE LOAD
DRIVE
The common emitter output stage adds rail-to-rail output
performance and is compensated to drive 35 pF (30% overshoot
at G = +1). Additional capacitance can be driven if a small snub
resistor is put in series with the capacitive load, effectively
decoupling the load from the output stage, as shown in Figure 12.
The output stage can source and sink 20 mA of current within
500 mV of the supply rails and 1 mA within 100 mV of the
supply rails.
INPUT OVERDRIVE
An additional feature of the AD8033/AD8034 is a bipolar input
pair that adds rail-to-rail common-mode input performance
specifically for applications that cannot tolerate phase inversion
problems.
Under normal common-mode operation, the bipolar input
pair is kept reversed, maintaining Ib at less than 1 pA. When
the input common-mode operation comes within 3.0 V of the
positive supply rail, I1 turns off and I4 turns on, supplying tail
current to the bipolar pair Q25 and Q27. With this configuration,
the inputs can be driven beyond the positive supply rail without
any phase inversion (see Figure 53).
As a result of entering the bipolar mode of operation, an offset
After re-entering the JFET common-mode range, the amplifier
recovers in approximately 100 ns (refer to Figure 29 for input
overload behavior). Above and below the supply rails, ESD
protection diodes activate, resulting in an exponentially
increasing input bias current. If the inputs are driven well
beyond the rails, series input resistance should be included
to limit the input bias current to <10 mA.
INPUT IMPEDANCE
The input capacitance of the AD8033/AD8034 forms a pole
with the feedback network, resulting in peaking and ringing
in the overall response. The equivalent impedance of the
feedback network should be kept small enough to ensure that
the parasitic pole falls well beyond the 3 dB bandwidth of the
gain configuration being used. If larger impedance values are
desired, the amplifier can be compensated by placing a small
capacitor in parallel with the feedback resistor. Figure 13 shows
the improvement in frequency response by including a small
feedback capacitor with high feedback resistance values.
THERMAL CONSIDERATIONS
Because the AD8034 operates at up to ±12 V supplies in the
small 8-lead SOT-23 package (160°C/W), power dissipation can
easily exceed package limitations, resulting in permanent shifts
in device characteristics and even failure. Likewise, high supply
voltages can cause an increase in junction temperature even
with light loads, resulting in an input bias current and offset
drift penalty. The input bias current doubles for every 10°C
shown in Figure 31. Refer to the Maximum Power Dissipation
section for an estimation of die temperature based on load and
supply voltage.
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