參數(shù)資料
型號(hào)： AD8037ARZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/24頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP VF ULDIST LN 70MA 8SOIC
標(biāo)準(zhǔn)包裝： 750
系列： CLAMPIN™
放大器類(lèi)型： 電壓反饋
電路數(shù)： 1
轉(zhuǎn)換速率： 1500 V/µs
-3db帶寬： 270MHz
電流 - 輸入偏壓： 3µA
電壓 - 輸入偏移： 2000µV
電流 - 電源： 18.5mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： ±3 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
配用： AD8037-EB-ND - BOARD EVAL FOR AD8037
AD8036/AD8037
REV. B
–21–
Layout Considerations
The specified high speed performance of the AD8036 and
AD8037 requires careful attention to board layout and component
selection. Proper RF design techniques and low pass parasitic
component selection are mandatory.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply and input clamp
bypassing (see Figure 17). One end should be connected to
the ground plane and the other within 1/8 inch of each power
and clamp pin. An additional large (0.47
F–10 F) tantalum
electrolytic capacitor should be connected in parallel, though
not necessarily so close, to supply current for fast, large signal
changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50
or 75 and be properly termi-
nated at each end.
Evaluation Board
An evaluation board for both the AD8036 and AD8037 is
available that has been carefully laid out and tested to demon-
strate that the specified high speed performance of the device
can be realized. For ordering information, please refer to the
Ordering Guide.
The layout of the evaluation board can be used as shown or
serve as a guide for a board layout.
IN
RO
1k
VOUT
0.1 F
AD8036/
AD8037
VH
0.1 F
VL
RS
–VS
+VS
–VS
+VS
RG
RF
1k
–VS
+VS
RT
NONINVERTING CONFIGURATION
C5
10 F
+VS
–VS
C3
0.1 F
C1
0.01 F
C6
10 F
C4
0.1 F
C2
0.01 F
OPTIONAL
SUPPLY BYPASSING
Figure 17. Noninverting Configurations for Evaluation
Boards
Table I.
AD8036A
AD8037A
Gain
Component
+1
+2
+10
+100
+2
+10
+100
RF
140
274
2 k
2 k
274
2 k
2 k
RG
274
221
20.5
274
221
20.5
RO (Nominal)
49.9
49.9
49.9
49.9
49.9
49.9
49.9
RS
130
100
100
100
100
100
100
RT (Nominal)
49.9
49.9
49.9
49.9
49.9
49.9
49.9
Small Signal BW (MHz)
240
90
10
1.3
275
21
3
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