參數(shù)資料
型號(hào)： AD8045ARDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/25頁(yè)
文件大小： 0K
描述： IC OPAMP VF ULDIST LN 70MA 8SOIC
產(chǎn)品培訓(xùn)模塊： Practical Guide High Speed PCB Layout
標(biāo)準(zhǔn)包裝： 98
放大器類(lèi)型： 電壓反饋
電路數(shù)： 1
轉(zhuǎn)換速率： 1350 V/µs
-3db帶寬： 1GHz
電流 - 輸入偏壓： 2µA
電壓 - 輸入偏移： 200µV
電流 - 電源： 16mA
電流 - 輸出 / 通道： 70mA
電壓 - 電源，單路/雙路(±)： 3.3 V ~ 12 V，±1.65 V ~ 6 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm Width）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 8-SOIC-EP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 769 (CN2011-ZH PDF)
AD8045
Rev. A | Page 23 of 24
EXPOSED PADDLE
The AD8045 features an exposed paddle, which lowers the
thermal resistance by 25% compared to a standard SOIC plastic
package. The exposed paddle of the AD8045 is internally con-
nected to the negative power supply pin. Therefore, when laying
out the board, the exposed paddle must either be connected to
the negative power supply or left floating (electrically isolated).
Soldering the exposed paddle to the negative power supply metal
ensures maximum thermal transfer. Figure 74 and Figure 75 show
the proper layout for connecting the SOIC and LFCSP exposed
paddle to the negative supply.
04814-0-071
Figure 74. SOIC Exposed Paddle Layout
The use of thermal vias or “heat pipes” can also be incorporated
into the design of the mounting pad for the exposed paddle.
These additional vias help to lower the overall theta junction to
ambient (θJA). Using a heavier weight copper on the surface to
which the amplifier’s exposed paddle is soldered can greatly
reduce the overall thermal resistance “seen” by the AD8045.
04814-0-073
Figure 75. LFCSP Exposed Paddle Layout
For existing designs that want to incorporate the AD8045,
electrically isolating the exposed paddle is another option. If the
exposed paddle is electrically isolated, the thermal dissipation is
primarily through the leads, and the thermal resistance of the
package now approaches 125°C/W, the standard SOIC θJA.
However, a thermally conductive and electrically isolated pad
material may be used. A thermally conductive spacer, such as
the Bergquist Company’s Sil-Pad, is an excellent solution to this
problem. Figure 76 shows a typical implementation using
thermal pad material.
04814-0-072
THERMAL CONDUCTIVE INSULATOR
Figure 76. SOIC with Thermal Conductive Pad Material
The thermal pad provides high thermal conductivity but
isolates the exposed paddle from ground or other potential. It is
recommended, when possible, to solder the paddle to the nega-
tive power supply plane or trace for maximum thermal transfer.
Note that soldering the paddle to ground shorts the negative
power supply to ground and can cause irreparable damage to
the AD8045.
DRIVING CAPACITIVE LOADS
In general, high speed amplifiers have a difficult time driving
capacitive loads. This is particularly true in low closed-loop
gains, where the phase margin is the lowest. The difficulty arises
because the load capacitance, CL, forms a pole with the output
resistance, RO, of the amplifier. The pole can be described by the
equation
L
O
P
C
R
f
2π
1
=
If this pole occurs too close to the unity gain crossover point,
the phase margin degrades. This is due to the additional phase
loss associated with the pole.
The AD8045 output can drive 18 pF of load capacitance directly,
in a gain of +2 with 30% overshoot, as shown in Figure 37.
Larger capacitance values can be driven but must use a snub-
bing resistor (RSNUB) at the output of the amplifier, as shown in
Figure 61 and Figure 62. Adding a small series resistor, RSNUB,
creates a zero that cancels the pole introduced by the load
capacitance. Typical values for RSNUB can range from 25 to
50 . The value is typically arrived at empirically and based on
the circuit requirements.
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