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參數(shù)資料
| 型號： | AD807A-155BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RECEIVER FIBER OPTIC 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 接收器 |
| 驅(qū)動器/接收器數(shù)： | 0/1 |
| 規(guī)程： | SDHj Sonet |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
REV. B
AD807
–7–
RMS JITTER – Degrees
30
0
1.4
2.3
1.5
PERCENT
A
G
E
–
%
1.6
1.7
1.8
2.2
20
5
15
25
10
1.9
2.0
2.1
TEST CONDITIONS
WORST-CASE:
–40 C, 4.5V
TPC 7. Output Jitter Histogram
FREQUENCY – Hz
1E+3
100E–3
10E+0
10E+6
JITTER
T
O
LERANCE
–
UI
10E+0
100E+0
1E+3
10E+3
100E+3
100E+0
1E+0
1E+6
AD807
SONET MASK
TPC 8. Jitter Tolerance
NOISE – V p-p @ 311MHz
3.0
0
0.6
0.1
JITTER
–
ns
p-p
0.2
0.3
0.4
0.5
2.0
1.0
0.7
0.8
0.9
PSR – NO FILTER
CMR
PSR – WITH FILTER
TPC 9. Output Jitter vs. Supply Noise and
Output Jitter vs. Common Mode Noise
THEORY OF OPERATION
Quantizer
The quantizer (comparator) has three gain stages, providing a
net gain of 350. The quantizer takes full advantage of the Extra
Fast Complementary Bipolar (XFCB) process. The input stage
uses a folded cascode architecture to virtually eliminate pulse
width distortion, and to handle input signals with common-
mode voltage as high as the positive supply. The input offset
voltage is factory trimmed and guaranteed to be less than 500
V.
XFCB’s dielectric isolation allows the different blocks within
this mixed-signal IC to be isolated from each other, hence the
2 mV Sensitivity is achieved. Traditionally, high speed compara-
tors are plagued by crosstalk between outputs and inputs, often
resulting in oscillations when the input signal approaches 10 mV.
The AD807 quantizer toggles at
±650 V (1.3 mV sensitivity) at
the input without making bit errors. When the input signal is
lowered below
± 650 V, circuit performance is dominated by
input noise, and not crosstalk.
0.1 F
FERRITE BEAD
OPTIONAL FILTER
0.1 F
50
309
50
3.65k
+5V
10 F
CHOKE
“BIAS TEE”
311MHz
NOISE
INPUT
0.1 F
500
13
12
14
11
6
3
PIN
NIN
AVCC2
AVCC1
VCC1
VCC2
AD807
0.1 F
QUANTIZER
INPUT
Figure 6. Power Supply Noise Sensitivity Test Circuit
0.1 F
50
309
50
3.65k
+5V
10 F
CHOKE
“BIAS TEE”
311MHz
NOISE
INPUT
0.1 F
500
13
12
14
11
6
3
PIN
NIN
AVCC2
AVCC1
VCC1
VCC2
AD807
0.1 F
QUANTIZER
INPUT
Figure 7. Common-Mode Rejection Test Circuit
Signal Detect
The input to the signal detect circuit is taken from the first stage
of the quantizer. The input signal is first processed through a gain
stage. The output from the gain stage is fed to both a positive
and a negative peak detector. The threshold value is subtracted
from the positive peak signal and added to the negative peak signal.
The positive and negative peak signals are then compared. If the
positive peak, POS, is more positive than the negative peak,
NEG, the signal amplitude is greater than the threshold, and the
output, SDOUT, will indicate the presence of signal by remain-
ing low. When POS becomes more negative than NEG, the
signal amplitude has fallen below the threshold, and SDOUT
will indicate a loss of signal (LOS) by going high. The circuit
provides hysteresis by adjusting the threshold level higher by a
factor of two when the low signal level is detected. This means
that the input data amplitude needs to reach twice the set LOS
threshold before SDOUT will signal that the data is again valid.
This corresponds to a 3 dB optical hysteresis.
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