參數(shù)資料
型號(hào)： AD807A-155BRZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/12頁(yè)
文件大?。?/td> 0K
描述： IC RECEIVER FIBER OPTIC 16SOIC
標(biāo)準(zhǔn)包裝： 2,500
類型： 接收器
驅(qū)動(dòng)器/接收器數(shù)： 0/1
規(guī)程： SDHj Sonet
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 帶卷 (TR)
REV. B
–12–
C00862–0–12/00
(rev.
B)
PRINTED
IN
U.S.A.
AD807
USING THE AD807
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10
F capacitor between V
CC and ground is recom-
mended. Care should be taken to isolate the 5 V power trace to
VCC2 (Pin 3). The VCC2 pin is used inside the device to provide
the CLKOUT and DATAOUT signals.
Use of 0.1
F capacitors between IC power supply and ground
is recommended. Power supply decoupling should take place as
close to the IC as possible. Refer to the schematic, Figure 12,
for recommended connections.
Transmission Lines
Use of 50
transmission lines are recommended for PIN, NIN,
CLKOUT, and DATAOUT signals.
Terminations
Termination resistors should be used for PIN, NIN, CLKOUT,
and DATAOUT signals. Metal, thick film, 1% tolerance resistors
are recommended. Termination resistors for the PIN, NIN signals
should be placed as close as possible to the PIN, NIN pins.
Connections from 5 V to load resistors for PIN, NIN, CLKOUT,
and DATAOUT signals should be individual, not daisy chained.
This will avoid crosstalk on these signals.
Loop Damping Capacitor, CD
A ceramic capacitor may be used for the loop damping capaci-
tor. Using a 0.15
F, +20% capacitor for a damping factor of
five provides < 0.1 dB jitter peaking.
AD807 Output Squelch Circuit
A simple P-channel FET circuit can be used in series with the
Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and
data outputs when SDOUT indicates a loss of signal (Figure 20).
The VCC2 supply pin draws roughly 61 mA (14 mA for each of 4
ECL loads, plus 5 mA for all 4 ECL output stages). This means
that selection of a FET with ON RESISTANCE of 0.5
will
affect the common mode of the ECL outputs by only 31 mV.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AD807
DATAOUTN
DATAOUTP
VCC2
CLKOUTN
CLKOUTP
VCC1
CF1
CF2
VEE
SDOUT
AVCC2
PIN
NIN
AVCC1
THRADJ
AVEE
P_FET
5V
BYPASS
CAP
TO VCC1, AVCC, AVCC2
Figure 20. Squelch Circuit Schematic
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Small Outline IC Package
(R-16A)
16
9
8
1
0.1574 (4.00)
0.1497 (3.80)
0.3937 (10.00)
0.3859 (9.80)
0.050 (1.27)
BSC
PIN 1
0.2440 (6.20)
0.2284 (5.80)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
8
0
0.0196 (0.50)
0.0099 (0.25)
45
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
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