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參數(shù)資料
| 型號： | AD807A-155BRZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RECEIVER FIBER OPTIC 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 接收器 |
| 驅(qū)動器/接收器數(shù)： | 0/1 |
| 規(guī)程： | SDHj Sonet |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
REV. B
AD807
–5–
Bandwidth
This describes the frequency at which the AD807 attenuates
sinusoidal input jitter by 3 dB.
Peaking
This describes the maximum jitter gain of the AD807 in dB.
Damping Factor,
ζ
Damping factor,
ζ describes the compensation of the second
order PLL. A larger value of
ζ corresponds to more damping
and less peaking in the jitter transfer function.
Acquisition Time
This is the transient time, measured in bit periods, required for
the AD807 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100
× on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit Error Rate vs. Signal-to-Noise Ratio
AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is
shown in TPC 6. Wideband amplitude noise is summed with
the input data signal as shown in Figure 4. Performance is
shown for input data levels of 5 mV and 10 mV.
VCM
2mV p-p
SCOPE
PROBE
AD807 QUANTIZER
EPITAXX ERM504
VCM
BINARY
OUTPUT
a. Single-Ended Input Application
VCM
1mV p-p
SCOPE
PROBE
AD807 QUANTIZER
AD8015
DIFFERENTIAL
OUTPUT TIA
VCM
BINARY
OUTPUT
+OUT
–OUT
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
+
50
0.47 F
75
1.0 F
100
GND
5V
+
–
POWER
COMBINER
POWER
COMBINER
PIN
NIN
DIFFERENTIAL
SIGNAL
SOURCE
POWER
SPLITTER
NOISE
SOURCE
FILTER
100MHz
D.U.T.
AD807
Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio
Test: Block Diagram
VBE 0.8V
AVCC2
DIFFERENTIAL
INPUT
CURRENT SOURCES
HEADROOM
0.7V
0.5mA
1mA
0.5mA
AVEE
400
a. Quantizer Differential Input Stage
5.9k
1.2V +VBE
AVEE
THRADJ
94.6k
b. Threshold Adjust
150
VEE
SDOUT
150
VCC1
IOH
IOL
c. Signal Detect Output (SDOUT)
450
VCC2
DIFFERENTIAL
INPUT
2.5mA
VEE
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 5. (a–d) Simplified Schematics
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| AD807A-155BRZRL7 | 功能描述:IC RECEIVER FIBER OPTIC 16SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD807ACHIPS | 功能描述:0/1 Receiver SDH Sonet Die 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):上次購買時間 類型:接收器 協(xié)議:SDH 同步光網(wǎng)絡(luò) 驅(qū)動器/接收器數(shù):0/1 雙工:- 接收器滯后:- 數(shù)據(jù)速率:- 電壓 - 電源:4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:- 供應(yīng)商器件封裝:模具 標(biāo)準(zhǔn)包裝:1 |
| AD808-622BR | 功能描述:IC FIBER OPTIC RCVR 16-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD808-622BRRL | 功能描述:IC FIBER OPTIC RCVR 16-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD808-622BRRL7 | 制造商:Analog Devices 功能描述:Fiber Optic Receiver 16-Pin SOIC N T/R 制造商:Rochester Electronics LLC 功能描述:FIBER OPTIC RECEIVER - 622 MBPS - Bulk |
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