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參數(shù)資料
| 型號： | AD808 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming(具有量化器和時鐘恢復和數(shù)據(jù)再定時功能的光纖接收器) |
| 中文描述： | 光纖接收器與量化和時鐘恢復和數(shù)據(jù)重定時（具有量化器和時鐘恢復和數(shù)據(jù)再定時功能的光纖接收器） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 116K |
| 代理商： | AD808 |
AD808
REV. 0
–5–
Damping Factor,
ζ
Damping factor,
ζ
describes the compensation of the second
order PLL. A larger value of
ζ
corresponds to more damping
and less peaking in the jitter transfer function.
Acquisition T ime
T his is the transient time, measured in bit periods, required for
the AD808 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100
×
on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
BINARY
OUTPUT
SCOPE
PROBE
AD808 QUANTIZER
V
CM
V
CM
4mVp-p
INPUT
a. Single-Ended Input Application
BINARY
OUTPUT
SCOPE
PROBE
AD808 QUANTIZER
V
CM
V
CM
2mVp-p
+INPUT
–INPUT
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
500
V
500
V
5k
V
5k
V
AV
EE
AV
CC
OUT
PIN
NIN
a. Quantizer Differential Input Stage
6k
V
THRADJ
AV
EE
80k
V
1.2V +V
BE
b. Threshold Adjust
30
V
V
CC1
SDOUT
V
EE
I
OL
I
OH
30
V
c. Signal Detect Output (SDOUT)
140
V
140
V
V
CC2
DIFFERENTIAL
OUTPUT
V
EE
7.8mA
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 4. (a–d) Simplified Schematics
T he AD808 has internal circuits to set the common-mode volt-
age at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as
shown in Figure 4a. T his allows very simple capacitive coupling
of the signal from the preamp in the AD808 as shown in Figure
3. T he internal common-mode potential is a diode drop (ap-
proximately 0.8 V) below the positive supply as shown in Figure
4a. Since the common mode is referred to the positive supply, it
is useful to bypass the common mode of the preamp to the
positive supply as well, if this is an option. Note, it is not neces-
sary to use capacitive coupling of the input signal with the
AD808. Figure 14 shows the input common-mode voltage can
be externally set.
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