參數(shù)資料
型號(hào)： AD8142ACPZ-RL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO AMP TRPL DIFF 24LFCSP
標(biāo)準(zhǔn)包裝： 5,000
應(yīng)用： 驅(qū)動(dòng)器
輸出類(lèi)型： 差分
電路數(shù)： 3
-3db帶寬： 285MHz
轉(zhuǎn)換速率： 1250 V/µs
電流 - 電源： 47mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 5.5 V，±2.25 V ~ 2.75 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-WQ（4x4）
包裝： 帶卷 (TR)
Data Sheet
AD8141/AD8142
Rev. A | Page 15 of 24
THEORY OF OPERATION
The differential drivers contained in the AD8141 and AD8142
differ from conventional op amps in that they have two outputs
whose voltages move in opposite directions. Like op amps, they
rely on high open-loop gain and negative feedback to force these
outputs to the desired voltages. The AD8141 and AD8142
drivers make it easy to perform single-ended-to-differential
conversion, common-mode level-shifting, and amplification
of differential signals.
Previous differential drivers, both discrete and integrated designs,
have been based on using two independent amplifiers and two
independent feedback loops, one to control each of the outputs.
When these circuits are driven from a single-ended source, the
resulting outputs are typically not well balanced. Achieving a
balanced output has generally required exceptional matching
of the amplifiers and feedback networks.
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the
use of a third amplifier and feedback loop to control the output
common-mode level. Sometimes, the third amplifier has also
been used to attempt to correct an inherently unbalanced circuit.
Excellent performance over a wide frequency range has proven
difficult with this approach.
Each AD8141/AD8142 driver uses two feedback loops to
separately control the differential and common-mode output
voltages. The differential feedback, set by the internal resistors,
controls the differential output voltage only. The internal common-
mode feedback loop controls the common-mode output voltage
only. This architecture makes it easy to arbitrarily set the output
common-mode level by simply applying a voltage to the VOCM
input. The output common-mode voltage is forced, by internal
common-mode feedback, to equal the voltage applied to the VOCM
input, while simultaneously balancing the differential output voltage.
The AD8141 VOCM inputs are available to the user, whereas the
AD8142 VOCM inputs are internally connected to sync-on-common-
mode circuitry that automatically imbeds the HSYNC and VSYNC
signals on the three output common-mode voltages.
The overall driver architecture produces outputs that are highly
balanced over a wide frequency range without requiring external
components or adjustments. The common-mode feedback loop
forces the signal component of the output common-mode voltage
to be zeroed. The result is nearly perfectly balanced differential
outputs of identical amplitude that are 180° apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The drivers use two negative feedback loops, each with high
open-loop gain, to force their differential and common-mode
output voltages in such a way as to minimize the differential
and common-mode input error voltages. The differential input
error voltage is defined as the voltage between the differential
inputs labeled VAP and VAN in Figure 36. For most purposes, this
voltage can be assumed to be zero. Similarly, the difference between
the actual output common-mode voltage and the voltage applied to
VOCM can also be assumed to be zero. Starting from these two
assumptions, any application circuit can be analyzed.
CLOSED-LOOP GAIN
The differential mode gain of the circuit in Figure 36 can be
described by
2
=
G
F
dm
IN,
dm
OUT,
R
V
where RF = 2.0 k and RG = 1.0 k nominally.
09461-
034
RF
RG
VAP
VAN
RG
RF
RL, dm
VOUT, dm
VON
VOP
VOCM
VIN, dm
VIP
VIN
+
–
Figure 36. Circuit Definitions
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
The effective input impedance of a circuit such as that in Figure 36
at VIP and VIN depends on whether the amplifier is being driven
by a single-ended or differential signal source. For balanced
differential input signals, the differential input impedance, RIN,dm
between the inputs VIP and VIN is simply
RIN, dm = 2 × RG = 2.0 k
In the case of a single-ended input signal (for example, if VIN
is grounded and the input signal is applied to VIP), the input
impedance becomes
(
)
kΩ
5
.
1
2
1
=
+
×
=
F
G
F
G
IN
R
The input impedance of the circuit is higher than for a
conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
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參數(shù)描述
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AD8143ACPZ-REEL7 功能描述:IC RECEIVER TRIPLE DIFF 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件
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