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參數(shù)資料
| 型號(hào)： | AD8142ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO AMP TRPL DIFF 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 應(yīng)用： | 驅(qū)動(dòng)器 |
| 輸出類型： | 差分 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 285MHz |
| 轉(zhuǎn)換速率： | 1250 V/µs |
| 電流 - 電源： | 47mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-WQ（4x4） |
| 包裝： | 帶卷 (TR) |
Data Sheet
AD8141/AD8142
Rev. A | Page 17 of 24
The desired differential output in this example is 1.4 V p-p
because the terminated input signal is 0.7 V p-p and the closed-
loop gain = 2. The actual differential output voltage is equal to
(0.725 V p-p)(2 k/1038.3 ) = 1.4 V p-p. This illustrates how
the two aforementioned effects cancel for large RF and RG.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output impedance of
the drivers to reduce phase margin, resulting in high frequency
ringing in the pulse response. The best way to minimize this effect
is to place the source termination resistors immediately at the
amplifier outputs to minimize parasitic capacitances formed by
unnecessarily long traces.
DISABLE
The AD8141 and AD8142 have disable pins that, when pulled high,
significantly reduce the power consumed while simultaneously
placing the outputs in high-Z states. The disable feature can be
used to multiplex two drivers. See Figure 17, Figure 19, and
Figure 22 for the disabled input-to-output isolation, output
impedance, and response performance. The threshold levels
for the disable pin are listed in Table 1.
An output glitch occurs whenever the disable feature is asserted or
deasserted. See the Applications Information section for details.
AD8142 SYNC-ON-COMMON-MODE
The AD8142 includes on-chip, sync-on-common-mode circuitry
that encodes externally applied HSYNC and VSYNC signals onto the
common-mode output voltages of each of the R, G, and B drivers.
The circuit encodes the horizontal and vertical sync pulses in a
way that results in low radiated energy. A simplified circuit that
illustrates how the pulses are encoded is shown in Figure 41.
For a more detailed description of the sync scheme, see the
Applications Information section.
The sync-on-common-mode circuit generates a current based
on the voltage applied to the SYNC LEVEL input pin (Pin 18)
with respect to the negative supply. With SYNC LEVEL input
tied to VS, the common-mode output of all drivers is set at 1.5 V
above the negative supply. Using a resistor divider, a voltage can
be applied between VS and SYNC LEVEL that determines the
maximum deviation of the common-mode outputs from their
midsupply level. If, for instance, SYNC LEVEL VS = 0.5 V
and the supply voltage is 5 V, then the common-mode outputs
fall within an envelope of 1.5 V ± 0.5 V. The state of each VOUT,cm
output based on the HSYNC and VSYNC inputs is determined by
the equations defined in the Applications Information section.
For the positive supplies between 2.5 V and 5 V, the sync-on-
common-mode circuit can be used by directly applying standard
inputs adhere to standard logic thresholds (see Table 1 for the
exact levels). The HSYNC and VSYNC inputs, therefore, can be
driven directly off the output of a computer video card without
concern of being overdriven. The input path from the HSYNC and
VSYNC inputs to the switches in the current mode level-shifting
circuit are well matched to eliminate false switching transients. This
maximizes common-mode balance and minimizes radiated energy.
H
V
H
R
H
V
VS–
BLUE VOCM
SYNC LEVEL
HSYNC
VSYNC
VS+
H
V
H
R
V
MIRROR
V
RED VOCM
GREEN VOCM
09461-
039
Figure 41. Sync-On-Common-Mode Simplified Circuit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8142-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Triple Differential Drivers |
| AD8143 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed, Triple Differential Receiver with Comparators |
| AD8143ACPZ-R2 | 制造商:Analog Devices 功能描述:SP Amp DIFF Receiver Amp Triple 制造商:Analog Devices 功能描述:SP AMP DIFF RCVR AMP TRIPLE 12V/24V 32LFCSP EP - Tape and Reel 制造商:Analog Devices 功能描述:TRIPLE DIFFERENTIAL RECEIVER |
| AD8143ACPZ-REEL | 功能描述:IC RECEIVER TRIPLE DIFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| AD8143ACPZ-REEL7 | 功能描述:IC RECEIVER TRIPLE DIFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
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