參數(shù)資料
型號(hào)： AD8155ACPZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/36頁(yè)
文件大?。?/td> 0K
描述： IC MUX/DEMUX DUAL BUFFER 64LFCSP
標(biāo)準(zhǔn)包裝： 750
系列： XStream™
功能： 多路復(fù)用器/多路分解器
電路： 2 x 2:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 1.6 V ~ 3.6 V
電流 - 電源： 735mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD8155
Rev. 0 | Page 33 of 36
REGISTER MAP
All registers are port-level and global registers, unless otherwise noted.
Table 22. Register Definitions
Mnemonic
Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Reset
0x00
RESET
Switch
Control 1
0x01
LBC
LBB
LBA
Set to 0
SELAb/B[1]
SELAb/B[0]
0x00
Switch
Control 2
0x02
SEL4G
BICAST
0x00
Global
Squelch Ctrl
0x04
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
GSQLCH_ENB
Reserved;
set to 1
Reserved;
set to 1
Reserved;
set to 1
0x0F
Switch Core/
Headroom
0x05
TX_HEAD
ROOM_C
TX_HEAD
ROOM_B
TX_HEAD
ROOM_A
XCORE_ENB
0x01
Mode
0x0F
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved; set
to 0
Reserved;
set to 0
MODE[1]
MODE[0]
0x00
RXA Disable
0x40
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved
RXDIS A1
RXDIS A0
0x00
RXA EQ
Setting
0x41
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
AEQ[3]
AEQ[2]
AEQ[1]
AEQ[0]
0x00
RXA LOS
Control
0x51
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved; set
to 0
LOS_FILT
Reserved;
set to 0
LOS_ENB
0x05
RXA Lane 1/
RXA Lane 0
EQ Setting
0x421
A1EQ[3]
A1EQ[2]
A1EQ[1]
A1EQ[0]
A0EQ[3]
A0EQ[2]
A0EQ[1]
A0EQ[0]
0x00
RXA P/N
Swap
0x441
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved; set
to 0
Reserved;
set to 0
PNA1
PNA0
0x00
RXA LOS
Status
0x451
Reserved
LOSA1
sticky
LOSA0
sticky
Reserved
LOSA1
active
LOSA0
active
TXA Disable
0x48
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved
TXDIS A1
TXDIS A0
0x00
TXA Level/PE
Control
0x49
ALEV[1]
ALEV[0]
APE[2]
APE[1]
APE[0]
0x20
TXA Lane1/
TXA Lane 0
PE Setting
0x4A1
A1PE[2]
A1PE[1]
A1PE[0]
A0PE[2]
A0PE[1]
A0PE[0]
0x00
TXA Per-Lane
Level Setting
0x4C1
Reserved
A1OLEV[1]
A1OLEV[0]
A0OLEV[1]
A0OLEV[0]
0xAA
RXB Disable
0x80
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved
RXDIS B1
RXDIS B0
0x00
RXB EQ
Setting
0x81
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
BEQ[3]
BEQ[2]
BEQ[1]
BEQ[0]
0x00
RXB LOS Ctrl
0x91
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved; set
to 0
LOS_FILT
Reserved;
set to 0
LOS_ENB
0x05
RXB Lane 1/
RXB Lane 0
EQ Setting
0x821
B1EQ[3]
B1EQ[2]
B1EQ[1]
B1EQ[0]
B0EQ[3]
B0EQ[2]
B0EQ[1]
B0EQ[0]
0x00
RXB P/N
Swap
0x841
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved; set
to 0
Reserved;
set to 0
PNB1
PNB0
0x00
RXB LOS
Status
0x851
Reserved
LOSB1
sticky
LOSB0
sticky
Reserved
LOSB1
active
LOSB0
active
TXB Disable
0x88
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved
TXDIS B1
TXDIS B0
0x00
TXB Level/PE
Control
0x89
BLEV[1]
BLEV[0]
BPE[2]
BPE[1]
BPE[0]
0x20
TXB Lane1/
TXB Lane 0
PE Setting
0x8A1
B1PE[2]
B1PE[1]
B1PE[0]
B0PE[2]
B0PE[1]
B0PE[0]
0x00
TXB Per-Lane
Level Setting
0x8C1
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
B1OLEV[1]
B1OLEV[0]
B0OLEV[1]
B0OLEV[0]
0xAA
RXC Disable
0xC0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Reserved
RXDIS C1
RXDIS C0
0x00
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