參數(shù)資料
型號(hào)： AD8192ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大小： 0K
描述： IC SW MUX HDMI/DVI 2:1 56LFCSP
標(biāo)準(zhǔn)包裝： 1
功能： 開關(guān)，DVI/HDMI
電路： 1 x 2:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-EP（8x8）
包裝： 托盤
AD8192
Rev. 0 | Page 22 of 28
PCB LAYOUT GUIDELINES
The AD8192 switches two distinctly different types of signals,
both of which are required for HDMI and DVI video. These
signal groups require different treatment when laying out a PCB.
The first group of signals carries the AV data. HDMI/DVI video
signals are differential, unidirectional, and high speed (up to
2.25 Gbps). The channels that carry the video data must be
controlled impedance, terminated at the receiver, and capable of
operating up to at least 2.25 Gbps. It is especially important to
note that the differential traces that carry the TMDS signals
should be designed with a controlled differential impedance of
100 Ω. The AD8192 provides single-ended 50 Ω terminations
on-chip for both its inputs and outputs, and both the input and
output terminations can be enabled or disabled through the
serial interface. Transmitter termination is not fully specified by
the HDMI standard but its inclusion improves the overall system
signal integrity.
The AV data carried on these high speed channels is encoded
by a technique called transition minimized differential signaling
(TMDS) and in the case of HDMI, is also encrypted according to
the high bandwidth digital copy protection (HDCP) standard.
The second group of signals consists of low speed auxiliary
control signals used for communication between a source and a
sink. Depending upon the application, these signals can include
the DDC bus (this is an I2C bus used to send EDID information
and HDCP encryption keys between the source and the sink),
the CEC line, and the HPD line. These auxiliary signals are
bidirectional, low speed, and transferred over a single-ended
transmission line that does not need to have controlled impedance.
The primary concern with laying out the auxiliary lines is ensuring
that they conform to the I2C bus standard and do not have
excessive capacitive loading.
TMDS Signals
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data
interleaves with the video data; the DVI standard does not incor-
porate audio information. The fourth high speed differential pair
is used for the AV data-word clock and runs at one-tenth the
speed of the TMDS data channels.
The four high speed channels of each input of the AD8192 are
identical. No concession was made to lower the bandwidth of
the fourth channel for the pixel clock; therefore, any channel
can be used for any TMDS signal. An external 2 kΩ pull-down
resistor on the TMDS CLKN signal is recommended for
improved noise immunity as shown in Figure 30.
The AD8192 buffers the TMDS signals and the input traces can
be considered electrically independent of the output traces. In
most applications, the quality of the signal on the input TMDS
traces is more sensitive to the PCB layout. Regardless of the data
being carried on a specific TMDS channel, or whether the TMDS
line is at the input or the output of the AD8192, all four high
speed signals should be routed on a PCB in accordance with the
same RF layout guidelines.
Layout for the TMDS Signals
The TMDS differential pairs can be either microstrip traces
(routed on the outer layer of a board) or stripline traces (routed
on an internal layer of the board). If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PCB binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path; therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together to establish the required 100 Ω differ-
ential impedance. Leave enough space between the differential
pairs of a given group to prevent the n of one pair from coupling
to the p of another pair. For example, one technique is to make
the interpair distance 4 to 10 times wider than the intrapair
spacing.
Any one group of four TMDS traces (either Input A, Input B, or
the outputs) should have closely matched trace lengths to mini-
mize interpair skew. Severe interpair skew can cause the data on
the four different channels of a group to arrive out of alignment
with one another. A good practice is to match the trace lengths
for a given group of four channels to within 0.05 inches on FR4
material.
Minimizing intrapair and interpair skew becomes increasingly
important as data rates increase. Any introduced skew consti-
tutes a correspondingly larger fraction of a bit period at higher
data rates.
Though the AD8192 features input equalization and output pre-
emphasis, minimizing the length of the TMDS traces is needed
to reduce overall system signal degradation. Commonly used
PCB material, such as FR4, is lossy at high frequencies, there-
fore, long traces on the circuit board increase signal attenuation,
resulting in decreased signal swing and increased jitter through
intersymbol interference (ISI).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD8192ACPZ-RL7 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR)
AD8192-EVALZ 制造商:AD 制造商全稱:Analog Devices 功能描述:2:1 HDMI/DVI Switch with Equalization and DDC/CEC Buffers
AD8192XCPZ 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):上次購(gòu)買時(shí)間 類型:視頻開關(guān) 應(yīng)用:HDTV，投影儀，機(jī)頂盒 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商器件封裝:56-LFCSP-VQ（8x8） 標(biāo)準(zhǔn)包裝:1
AD8192XCPZ-RL 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購(gòu)買時(shí)間 類型:視頻開關(guān) 應(yīng)用:HDTV，投影儀，機(jī)頂盒 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商器件封裝:56-LFCSP-VQ（8x8） 標(biāo)準(zhǔn)包裝:1
AD8193 制造商:AD 制造商全稱:Analog Devices 功能描述:Buffered 2:1 TMDS Switch
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