參數(shù)資料
型號(hào)： AD8192ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 0K
描述： IC SW MUX HDMI/DVI 2:1 56LFCSP
標(biāo)準(zhǔn)包裝： 1
功能： 開(kāi)關(guān)，DVI/HDMI
電路： 1 x 2:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-EP（8x8）
包裝： 托盤(pán)
AD8192
Rev. 0 | Page 23 of 28
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on
a number of variables including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask. There are
many combinations that can produce the correct characteristic
impedance. Generally, working with the PCB fabricator is
required to obtain a set of parameters to produce the desired
results.
One consideration is how to guarantee a differential pair with
a differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential pair
are close and strongly coupled, they should have a width that
produces a100 Ω differential impedance. When the traces split
apart to go into a connector, for example, and are no longer so
strongly coupled, the width of the traces needs to be increased
to yield a differential impedance of 100 Ω in the new configuration.
Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the AD8192. This requires a designer to route the
TMDS traces on multiple layers of the PCB. When routing dif-
ferential pairs on multiple layers, it is necessary to also reroute
the corresponding reference plane to provide one continuous
ground current return path for the differential signals. Standard
plated through-hole vias are acceptable for both the TMDS
traces and the reference plane. An example of this is illustrated
PCB DIELECTRIC
SILKSCREEN
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
LAYER 4: SIGNAL (MICROSTRIP)
THROUGH-HOLE VIAS
LAYER 1: SIGNAL (MICROSTRIP)
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
LAYER 3: PWR
(REFERENCE PLANE)
07
05
0-
03
2
Figure 33. Example Routing of Reference Plane
TMDS Terminations
The AD8192 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
The output termination resistors of the AD8192 back terminate
the output TMDS transmission lines. These back terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8192
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
Auxiliary Control Signals
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application. These are hot plug
detect (HPD), consumer electronics control (CEC), and two
display data channel (DDC) lines. The two signals on the DDC
bus are SDA and SCL (serial data and serial clock, respectively).
The DDC and CEC signals are buffered and switched through
the AD8192, and the HPD signal is pulsed low by the AD8192.
These signals do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8192 is being used.
For example, the maximum speed of signals present on the
auxiliary lines are 100 kHz I2C data on the DDC lines, therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
bus should suffice. The HDMI 1.3a specification, however,
places a strict 50 pF limit on the amount of capacitance that can
be measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8192, or an
equivalent receiver. There is a similar limit of 150 pF of input
capacitance for the CEC line. The benefit of the AD8192 is that
it buffers these lines, isolating the output capacitance so that
only the capacitance at the input side contributes to the speci-
fied limit. Good board design is still required, however.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stackup, relieving or clearing out this reference plane
immediately under the auxiliary traces significantly decreases
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD8192ACPZ-RL7 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開(kāi)關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR)
AD8192-EVALZ 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2:1 HDMI/DVI Switch with Equalization and DDC/CEC Buffers
AD8192XCPZ 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤(pán) 零件狀態(tài):上次購(gòu)買(mǎi)時(shí)間 類(lèi)型:視頻開(kāi)關(guān) 應(yīng)用:HDTV，投影儀，機(jī)頂盒 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商器件封裝:56-LFCSP-VQ（8x8） 標(biāo)準(zhǔn)包裝:1
AD8192XCPZ-RL 功能描述:IC SW MUX HDMI/DVI 2:1 56LFCSP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購(gòu)買(mǎi)時(shí)間 類(lèi)型:視頻開(kāi)關(guān) 應(yīng)用:HDTV，投影儀，機(jī)頂盒 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商器件封裝:56-LFCSP-VQ（8x8） 標(biāo)準(zhǔn)包裝:1
AD8193 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Buffered 2:1 TMDS Switch
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