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參數(shù)資料
| 型號： | AD8253ARMZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP INST ICMOS LDRIFT 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | iCMOS® |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 20 V/µs |
| -3db帶寬： | 10MHz |
| 電流 - 輸入偏壓： | 5nA |
| 電壓 - 輸入偏移： | 150µV |
| 電流 - 電源： | 4.6mA |
| 電流 - 輸出 / 通道： | 37mA |
| 電壓 - 電源，單路/雙路(±)： | ±5 V ~ 15 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
AD8253
Data Sheet
Rev. B | Page 16 of 24
THEORY OF OPERATION
10k
REF
OUT
A3
–IN
+IN
WR
1.2k
+VS
–VS
+VS
–VS
+VS
–VS
A1
A0
2.2k
DGND
A1
A2
DIGITAL
GAIN
CONTROL
2.2k
+VS
–VS
+VS
–VS
+VS
–VS
+VS
–VS
0
69
83
-0
61
Figure 51. Simplified Schematic
The AD8253 is a monolithic instrumentation amplifier based
on the classic 3-op-amp topology, as shown in Figure 51. It is
fabricated on the Analog Devices, Inc., proprietary iCMOS
process that provides precision linear performance and a robust
digital interface. A parallel interface allows users to digitally
program gains of 1, 10, 100, and 1000. Gain control is achieved
by switching resistors in an internal precision resistor array (as
shown in Figure 51).
All internal amplifiers employ distortion cancellation circuitry
and achieve high linearity and ultralow THD. Laser-trimmed
resistors allow for a maximum gain error of less than 0.03% for
G = 1 and a minimum CMRR of 100 dB for G = 1000. A pinout
optimized for high CMRR over frequency enables the AD8253
to offer a guaranteed minimum CMRR over frequency of 80 dB
at 20 kHz (G = 1). The balanced input reduces the parasitics
that in the past had adversely affected CMRR performance.
GAIN SELECTION
This section describes how to configure the AD8253 for basic
operation. Logic low and logic high voltage limits are listed in
the Specifications section. Typically, logic low is 0 V and logic
high is 5 V; both voltages are measured with respect to DGND.
Refer to the specifications table (Table 2) for the permissible
voltage range of DGND. The gain of the AD8253 can be set
using two methods: transparent gain mode and latched gain
mode. Regardless of the mode, pull-up or pull-down resistors
should be used to provide a well-defined voltage at the A0 and
A1 pins.
Transparent Gain Mode
The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1. Figure 52
shows an example of this gain setting method, referred to through-
out the data sheet as transparent gain mode. Tie WR to the
negative supply to engage transparent gain mode. In this mode,
any change in voltage applied to A0 and A1 from logic low to
logic high, or vice versa, immediately results in a gain change.
shows the AD8253 configured in transparent gain mode.
+15V
–15V
A0
A1
WR
+IN
+5V
–IN
10μF0.1F
G = 1000
DGND
REF
AD8253
NOTE:
1. IN TRANSPARENT GAIN MODE, WR IS TIED TO VS.
THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE
THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE
SET TO LOGIC HIGH, RESULTING IN A GAIN OF 1000.
0
69
83
-05
1
Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 1000
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