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參數(shù)資料
| 型號： | AD8253ARMZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大小： | 0K |
| 描述： | IC AMP INST ICMOS LDRIFT 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | iCMOS® |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 20 V/µs |
| -3db帶寬： | 10MHz |
| 電流 - 輸入偏壓： | 5nA |
| 電壓 - 輸入偏移： | 150µV |
| 電流 - 電源： | 4.6mA |
| 電流 - 輸出 / 通道： | 37mA |
| 電壓 - 電源，單路/雙路(±)： | ±5 V ~ 15 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
Data Sheet
AD8253
Rev. B | Page 17 of 24
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
A1
A0
Gain
VS
Low
1
VS
Low
High
10
VS
High
Low
100
VS
High
1000
Latched Gain Mode
Some applications have multiple programmable devices such
as multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8253 can be set using WR as a latch,
allowing other devices to share A0 and A1. Figure 53 shows a
schematic using this method, known as latched gain mode. The
AD8253 is in this mode when WR is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0 and A1
are read on the downward edge of the WR signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table listing
in Table 6 for more on these gain changes.
+15V
–15V
A0
A1
WR
+IN
–IN
10μF0.1F
DGND
REF
AD8253
A0
A1
WR
+5V
0V
G = PREVIOUS
STATE
G = 1000
+
–
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 1000.
06
98
3-
0
5
2
Figure 53. Latched Gain Mode, G = 1000
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
A1
A0
Gain
High to Low
Low
Change to 1
High to Low
Low
High
Change to 10
High to Low
High
Low
Change to 100
High to Low
High
Change to 1000
Low to Low
X1
No change
Low to High
X1
No change
High to High
X1
No change
1 X = don’t care.
On power-up, the AD8253 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8253 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 on power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, tSU, before the downward edge of WR
latches in the gain. Similarly, they must be held for a minimum
hold time, tHD, after the downward edge of WR to ensure that
the gain is latched in correctly. After tHD, A0 and A1 may change
logic levels, but the gain does not change until the next downward
edge of WR. The minimum duration that WR can be held high
is t WR-HIGH, and t WR-LOW is the minimum duration that WR can
be held low. Digital timing specifications are listed in Table 2.
The time required for a gain change is dominated by the settling
time of the amplifier. A timing diagram is shown in Figure 54.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8253. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.
A0, A1
WR
tSU
tHD
tWR-HIGH
tWR-LOW
0
69
83
-0
53
Figure 54. Timing Diagram for Latched Gain Mode
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