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參數(shù)資料
| 型號： | AD8305ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LOGARITH CONV 100DB 16-LFCSP |
| 設(shè)計(jì)資源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 對數(shù)轉(zhuǎn)換器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 550 (CN2011-ZH PDF) |
| 其它名稱： | AD8305ACPZ-RL7DKR |
AD8305
Rev. B | Page 21 of 24
EVALUATION BOARD
An evaluation board is available for the AD8305, the schematic for which is shown in Figure 49. It can be configured for a wide variety of
experiments. The buffer gain is factory-set to unity, providing a slope of 200 mV/decade, and the intercept is set to 1 nA. Table 4 describes
the various configuration options.
Table 4. Evaluation Board Configuration Options
Component
Function
Default Condition
P1
Supply interface. Provides access to supply pins, VNEG, COMM, and VPOS.
P1 = installed
P2, R8, R9, R10,
R11, R17, R18
Monitor Interface. By adding 0 Ω resistors to R8, R9, R10, R11, R17, and R18, the
VRDZ, VREF, VSUM, VOUT, and VLOG pin voltages can be monitored using a high
impedance probe.
P2 = Not installed
R8 = R9 = R10 = Open (size 0603)
R17 = R18 = Open (size 0603)
R2, R3, R4, R6,
R14, C2, C7, C9,
C10
Buffer amplifier/output interface. The logarithmic slope of the AD8305 can be
altered using the buffer’s gain-setting resistors, R2 and R3. R4, R14, and C2 allow
variation in the buffer loading. R6, C7, C9, and C10 are provided for a variety of
filtering applications.
R2 = R6 = 0 Ω (size 0603)
R3 = R4 = open (size 0603)
R11 = R14 = 0 Ω (size 0603)
C2 = C7 = open (size 0603)
C9 = C10 = open (size 0603)
VLOG = VOUT = installed
R1, R7, R19, R20
Intercept adjustment. The voltage dropped across resistor R1 determines the
intercept reference current, nominally set to 10 μA using a 200 kΩ 1% resistor. R7
and R19 can be used to adjust the output-offset voltage at the VLOG output.
R1 = 200 kΩ (size 0603)
R7 = R19 = 0 Ω (size 0603)
R20 = open (size 0603)
R12, R15, C3, C4,
C5, C6
Supply Decoupling.
C3 = C4 = 0.01 μF
(size 0603)
C5 = C6 = 0.1 μF (size 0603)
R12 = R15 = 0 Ω (size 0603)
C11
VSUM decoupling capacitor.
C11 = 1 nF (size 0603)
R13, R16, C1, C8
Input compensation. Provides essential HF compensation at the input pins, INPT
and IREF.
R13 = R16 = 1 kΩ (size 0603)
C1 = C8 = 1 nF (size 0603)
IREF, INPT, PD,
LK1, R5
Input interface. The test board is configured to accept a current through the SMA
connector labeled INPT. An SC-style packaged photodiode can be used in place
of the INPT SMA for optical interfacing. By removing R1 and adding a 0 Ω short
for R5, a second current can be applied to the IREF input (also SMA) for evaluating
the AD8305 in log-ratio applications.
IREF = INPT = installed
PD = not installed
LK1 = installed
R5 = open (size 0603)
J1
SC-Style Photodiode. Allows for direct mounting of SC style photodiodes.
J1 = not installed
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