The voltage, V" />
參數(shù)資料
型號(hào)： AD8305ACPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/24頁(yè)
文件大小： 0K
描述： IC LOGARITH CONV 100DB 16-LFCSP
設(shè)計(jì)資源： Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056)
Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 對(duì)數(shù)轉(zhuǎn)換器
應(yīng)用： 光纖
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP-VQ
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 550 (CN2011-ZH PDF)
其它名稱： AD8305ACPZ-RL7DKR
AD8305
Rev. B | Page 12 of 24
required to accommodate this situation (see the Using A
The voltage, VLOG, is generated by applying ILOG to an internal
resistance of 4.55 kΩ, formed by the parallel combination of a
6.69 kΩ resistor to ground and the 14.2 kΩ resistor to the
VRDZ pin. When the VLOG pin is unloaded and the intercept
repositioning is disabled by grounding VRDZ, the output
current, ILOG, generates a voltage at the VLOG pin of
VLOG = ILOG × 4.55 kΩ
= 44 μA × 4.55 kΩ × log10(IPD/IREF)
(5)
= VY log10(IPD/IREF)
where VY = 200 mV/decade, or 10 mV/dB. Note that any
resistive loading on VLOG lowers this slope and also result in
an overall scaling uncertainty due to the variability of the on-
chip resistors. Consequently, this practice is not recommended.
VLOG may also swing below ground when dual supplies (VP and
VN) are used. When VN = 0.5 V or larger, the input pins INPT
and IREF may now be positioned at ground level by simply
grounding VSUM.
MANAGING INTERCEPT AND SLOPE
When using a single supply, VRDZ should be directly connected to
VREF to allow operation over the entire five-decade input current
range. As noted previously, this introduces an accurate offset
voltage of 0.8 V at the VLOG pin, equivalent to four decades,
resulting in a logarithmic transfer function that can be written as
VLOG = VY log10(104 × IPD/IREF)
= VY log10 (IPD/IINTC)
(6)
where IINTC = IREF/104.
Thus, the effective intercept current IINTC is only one ten-
thousandth of IREF, corresponding to 1 nA when using the
recommended value of IREF = 10 mA.
The slope can be reduced by attaching a resistor to the VLOG
pin. This is strongly discouraged, in view of the fact that the on-
chip resistors do not ratio correctly to the added resistance. Also, it
is rare that one would want to lower the basic slope of 10 mV/dB; if
this is needed, it should be effected at the low impedance output
of the buffer, which is provided to avoid such miscalibration and
also allow higher slopes to be used.
The AD8305 buffer is essentially an uncommitted op amp with
rail-to-rail output swing, good load-driving capabilities, and a
unity-gain bandwidth of >12 MHz. In addition to allowing the
introduction of gain, using standard feedback networks and
thereby increasing the slope voltage VY, the buffer can be used
to implement multipole low-pass filters, threshold detectors,
and a variety of other functions. Further details of these can be
found in the AD8304 data sheet.
RESPONSE TIME AND NOISE CONSIDERATIONS
The response time and output noise of the AD8305 are
fundamentally a function of the signal current, IPD. For small
currents, the bandwidth is proportional to IPD, as shown in
Figure 15. The output low frequency voltage-noise spectral-
density is a function of IPD (Figure 17) and also increases for
small values of IREF. Details of the noise and bandwidth
performance of translinear log amps can be found in the
AD8304 data sheet.
POWER SUPPLY SEQUENCING
Some applications may result in the presence of large input
signal current (>1 mA) prior to the AD8305 being powered on.
In such cases, it is recommended that power supply sequencing
be implemented such that the AD8305 is powered on prior to
the photodiode or current source.
In those applications where it is not possible to implement
supply sequencing, VSUM should be driven externally by a low
impedance source. In applications where a low-impedance bias-
source is not readily available, the circuit shown in Figure 34
can be used.
+VBIAS
+VP
VPOS
VNEG
VSUM
2N2907
COMM
INPT
IPD
R1
03
05
3-
0
49
C1
RA
RB
IE
β
VBE
+
–
IC
≈0.5V
+VS
C2
Figure 34. VSUM Biasing Circuit for Applications Where Large Input Signals
Are Present Prior to AD8305 Power-On
The 2N2907 transistor used in Figure 34 is a common PNP-type
switching transistor. Ra and Rb are selected such that the voltage
at the base of the transistor is ~0.5 V.
In general, VS × [Rb/(Ra+Rb)] should equal approximately 0.5 V.
Setting Ra = 5 kΩ and Rb = 1 kΩ, results in 500 μA of additional
quiescent current for a 3 V supply under normal operation.
Larger resistor values may be used for this divider network by
choosing a transistor with a higher β than the 2N2907.
Given a typical Vbe of 0.7 V, the voltage at VSUM is ~1.2 V when
the AD8305 is off and a large input signal is being applied. Once
the AD8305 is powered on the voltage at VSUM is pulled down
to its nominal value of 0.5 V. The circuit in Figure 34 is tested
for 3 V to 5 V positive supplies over the full temperature range
for the AD8305. C1, and R1 are the components that make up
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