參數(shù)資料
型號(hào)： AD830ARZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 0K
描述： IC AMP VIDEO DIFF HS 8SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 差分
電路數(shù)： 1
-3db帶寬： 85MHz
轉(zhuǎn)換速率： 360 V/µs
電流 - 電源： 14.5mA
電流 - 輸出 / 通道： 50mA
電壓 - 電源，單路/雙路(±)： 8 V ~ 33 V，±4 V ~ 16.5 V
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
AD830
Rev. C | Page 13 of 20
10
0%
100
90
1V
00
88
1-
0
30
Figure 30. Clipping Behavior
Choice of Polarity
The sign of the gain is easily selected by choosing the polarity
of the connections to the + and inputs of the X GM stage.
Swapping between inverting and noninverting gain is possible
simply by reversing the input connections. The response of the
amplifier is identical in either connection, except for the sign
change.
The bandwidth, high impedance, and transient behavior of the
AD830 is symmetrical for both polarities of gain. This is very
advantageous and unlike an op amp.
Input Impedance
The relatively high input impedance of the AD830, for a
differential receiver amplifier, permits connections to modest
impedance sources without much loading or loss of common-
mode rejection. The nominal input resistance is 300 kΩ. The
real limit to the upper value of the source resistance is in its
effect on common-mode rejection and bandwidth. If the source
resistance is in only one input, then the low frequency
common-mode rejection is lowered to ≈ RIN/RS. The source
resistance/input capacitance pole limits the bandwidth. Refer to
the following equation:
×
π
=
IN
S
C
R
f
2
1
Furthermore, the high frequency common-mode rejection is
additionally lowered by the difference in the frequency response
caused by the RS × CIN pole. Therefore, to maintain good low
and high frequency common-mode rejection, it is recommended
that the source resistances of the + and inputs be matched and
of modest value (≤10 kΩ).
Handling Bias Currents
The bias currents are typically 4 μA flowing into each pin of the
GM stages of the AD830. Because all applications possess some
finite source resistance, the bias current through this resistor
creates a voltage drop (IBIAS × RS). The relatively high input
impedance of the AD830 permits modest values of RS, typically
≤10 kΩ. If the source resistance is in only one terminal, then an
objectionable offset voltage may result, for example, 4 μA × 5
kΩ = 20 mV. Placement of an equal value resistor in series with
mismatches in the resistances, a residual offset remains and is
likely to be greater than the bias current (offset current)
mismatches.
Applying Fee
the other input cancels the offset to first order. However, due to
dback
for use with gains from 1 to 100. Gains
hat
y
830 is defined by the differential
n
ge
e
The AD830 is intended
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 40) with gain >1.
The value of the bottom resistor, R2, should be kept less than
1 kΩ to ensure that the pole formed by CIN and the parallel
connection of R1 and R2 is sufficiently high in frequency so t
it does not introduce excessive phase shift around the loop and
destabilize the amplifier. A compensating resistor, equal to the
parallel combination of R1 and R2, should be placed in series
with the other Y GM stage input to preserve the high frequenc
common-mode rejection and to lower the offset voltage
induced by the input bias current.
Output Common Mode
The output swing of the AD
input voltage, the gain, and the output common. Depending o
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output volta
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus the supply is
shown in Figure 31. A prediction of the common-mode rang
versus the peak output differential voltage can be easily derived
from the maximum output swing as VOCM = VMAX VPEAK.
SUPPLY VOLTAGE (V)
15
0
20
0
MA
X
IMU
M
O
U
T
P
U
T
S
W
IN
G
(±
V
)
48
12
16
6
3
12
9
VP
VN
00
88
1-
0
31
Figure 31. Maximum Output Swing vs. Supply
Output Cur
output current is set by the short-circuit
nto
rent
The absolute peak
current limiting, typically greater than 60 mA. The maximum
drive capability is rated at 50 mA but without a guarantee of
distortion performance. Best distortion performance is obtained
by keeping the output current ≤20 mA. Attempting to drive
large voltages into low valued resistances, for example, 10 V i
150 Ω causes an apparent lowering of the limit for output signal
swing but is just the current limiting behavior.
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AD830JR 功能描述:IC VIDEO DIFF AMP HS 8-SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 視頻放大器和頻緩沖器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 應(yīng)用:驅(qū)動(dòng)器 輸出類型:差分 電路數(shù):3 -3db帶寬:350MHz 轉(zhuǎn)換速率:1000 V/µs 電流 - 電源:14.5mA 電流 - 輸出 / 通道:60mA 電壓 - 電源，單路/雙路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安裝類型:表面貼裝 封裝/外殼:20-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR)
AD830JR-REEL 功能描述:IC VIDEO DIFF AMP HS 8-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 視頻放大器和頻緩沖器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 應(yīng)用:驅(qū)動(dòng)器 輸出類型:差分 電路數(shù):3 -3db帶寬:350MHz 轉(zhuǎn)換速率:1000 V/µs 電流 - 電源:14.5mA 電流 - 輸出 / 通道:60mA 電壓 - 電源，單路/雙路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安裝類型:表面貼裝 封裝/外殼:20-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR)
AD830JR-REEL7 功能描述:IC VIDEO DIFF AMP HS 8-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 視頻放大器和頻緩沖器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 應(yīng)用:驅(qū)動(dòng)器 輸出類型:差分 電路數(shù):3 -3db帶寬:350MHz 轉(zhuǎn)換速率:1000 V/µs 電流 - 電源:14.5mA 電流 - 輸出 / 通道:60mA 電壓 - 電源，單路/雙路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安裝類型:表面貼裝 封裝/外殼:20-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR)
AD830JRZ 功能描述:IC VIDEO DIFF AMP HS 8-SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 視頻放大器和頻緩沖器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 應(yīng)用:驅(qū)動(dòng)器 輸出類型:差分 電路數(shù):3 -3db帶寬:350MHz 轉(zhuǎn)換速率:1000 V/µs 電流 - 電源:14.5mA 電流 - 輸出 / 通道:60mA 電壓 - 電源，單路/雙路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安裝類型:表面貼裝 封裝/外殼:20-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR)
AD830JRZ 制造商:Analog Devices 功能描述:IC VIDEO DIFF AMP 85MHZ 360V/US 8SO
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