VP VOUT
參數(shù)資料
型號: AD830ARZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 9/20頁
文件大?。?/td> 0K
描述: IC AMP VIDEO DIFF HS 8SOIC
標(biāo)準(zhǔn)包裝: 1,000
應(yīng)用: 差分
電路數(shù): 1
-3db帶寬: 85MHz
轉(zhuǎn)換速率: 360 V/µs
電流 - 電源: 14.5mA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): 8 V ~ 33 V,±4 V ~ 16.5 V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
AD830
Rev. C | Page 17 of 20
75
75
VP
VOUT
VN
AD830
1
2
3
4
8
7
6
5
A = 1
GM
C
0.1F
VIN
00
88
1-
0
4
Figure 44. Full Bandwidth Line Driver (G = +2)
SUPPLY VOLTAGE (±V)
0.05
0.01
5
1
5
D
IFF
E
R
E
N
TI
A
L
G
A
IN
(
%
)
1
2
1
73
1
0.04
0.06
0.07
0.09
4
GAIN
PHASE
GAIN = +2
RL = 150
FREQ = 3.58MHz
0 TO 0.7V
11
10
9
8
6
0.02
0.03
0.10
0.08
DI
F
E
R
E
N
T
IAL
P
HAS
E
(
D
eg
re
e
s
)
0.16
0.04
0.06
0.14
0.18
0.02
0.12
0.10
0.08
0.20
0
08
81
-04
5
FREQUENCY (Hz)
0.2
10k
A
M
P
L
IT
UDE
RE
S
P
O
NS
E
(
d
B)
–0.8
100k
1M
10M
100M
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
VS = ±15V
RL = 150
GAIN = +2
VS = ±10V
VS = ±5V
0
088
1-
0
46
Figure 46. 0.1 dB Gain Flatness for the Circuit of Figure 44
AC-COUPLED LINE RECEIVER
The AD830 is configurable as an ac-coupled differential
amplifier on a single- or bipolar-supply voltage. All that is
needed is inclusion of a few noncritical passive components, as
illustrated in Figure 47. A simple resistive network at the X GM
input establishes a common-mode bias. Here, the common
mode is centered at 6 V, but in principle can be any voltage
within the common-mode limits of the AD830. The 10 kΩ
resistors to each input bias the X GM stage with sufficiently high
impedance to keep the input coupling corner frequency low, but
not too large so that residual bias current induced offset voltage
becomes troublesome. For dual-supply operation, the 10 kΩ
resistors may go directly to ground. The output common is
conveniently set by a Zener diode for a low impedance
reference to preserve the high frequency CMR. However, a
simple resistive divider works fine, and good high frequency
CMR can be maintained by placing a compensating resistor in
series with the +Y input. The excellent CMRR response of the
circuit is shown in Figure 48. A plot of the 0.1 dB flatness from
10 Hz is also shown. With the use of 10 μF capacitors, the CMR
is >90 dB down to a few tens of hertz. This level of performance
is almost impossible to achieve with discrete solutions.
Figure 45. Differential Gain and Phase for the Circuit of Figure 44
75
75
+12V
VOUT
1000F
10F
AD830
1
2
3
4
8
7
6
5
A = 1
GM
C
0.1F
ZCM
75
COAX
CABLE
+12V
4.7k
6.8V
1N4736
INPUT
SIGNAL
RT
10k
10k
2k
*
+VS
10k
10k
*OPTIONAL TUNING FOR IMPROVING
VERY LOW FREQUENCY CMR.
00
88
1-
0
47
Figure 47. AC-Coupled Line Receiver
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