參數(shù)資料
型號: AD8370AREZ
廠商: Analog Devices Inc
文件頁數(shù): 5/28頁
文件大?。?/td> 0K
描述: IC AMP VGA DIFF LN 16TSSOP
產(chǎn)品培訓模塊: Differential Circuit Design Techniques for Communication Applications
標準包裝: 96
放大器類型: 可變增益
電路數(shù): 1
輸出類型: 差分
轉(zhuǎn)換速率: 5750 V/ns
-3db帶寬: 750MHz
電流 - 輸入偏壓: 400pA
電流 - 電源: 79mA
電壓 - 電源,單路/雙路(±): 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TSSOP-EP
包裝: 管件
產(chǎn)品目錄頁面: 775 (CN2011-ZH PDF)
Data Sheet
AD8370
Rev. B | Page 13 of 28
THEORY OF OPERATION
The AD8370 is a low cost, digitally controlled, fine adjustment
variable gain amplifier (VGA) that provides both high IP3 and
low noise figure. The AD8370 is fabricated on an ADI proprietary
high performance 25 GHz silicon bipolar process. The –3 dB
bandwidth is approximately 750 MHz throughout the variable
gain range. The typical quiescent current of the AD8370 is
78 mA. A power-down feature reduces the current to less than
4 mA. The input impedance is approximately 200 differential,
and the output impedance is approximately 100 differential
to be compatible with saw filters and matching networks used
in intermediate frequency (IF) radio applications. Because there
is no feedback between the input and output and stages within
the amplifier, the input amplifier is isolated from variations in
output loading and from subsequent impedance changes, and
excellent input to output isolation is realized. Excellent distortion
performance and wide bandwidth make the AD8370 a suitable
gain control device for modern differential receiver designs. The
AD8370 differential input and output configuration is ideally
suited to fully differential signal chain circuit designs, although
it can be adapted to single-ended system applications, if required.
BLOCK ARCHITECTURE
The three basic building blocks of the AD8370 are a high/low
gain selectable input preamplifier, a digitally controlled
transconductance (gm) block, and a fixed gain output stage.
INHI
INLO
OPHI
OPLO
VCCO
OCOM
ICOM
VOCM
PWUP
VCCO
OCOM
VCCI
ICOM
BIAS CELL
SHIFT REGISTER
AND LATCHES
PRE
AMP
TRANSCONDUCTANCE
OUTPUT
AMP
11
6
1
16
4
14
13
12
5
9
8
3
2
10
7
15
DATA CLCK LTCH
AD8370
03692-035
Figure 37. Functional Block Diagram
PREAMPLIFIER
There are two selectable input preamplifiers. Selection is made
by the most significant bit (MSB) of the serial gain control data-
word. In the high gain mode, the overall device gain is 7.1 V/V
(17 dB) above the low gain setting. The two preamplifiers give
the AD8370 the ability to accommodate a wide range of input
amplitudes. The overlap between the two gain ranges allows the
user some flexibility based on noise and distortion demands.
See the Choosing Between Gain Ranges section for more
information.
The input impedance is approximately 200 differential,
regardless of which preamplifier is selected. Note that the input
impedance is formed by using active circuit elements and is not
set by passive components. See Figure 38 for a simplified
schematic of the input interface.
1mA
VCC/2
2k
INHI/INLO
03692-
036
Figure 38. INHI/INLO Simplified Schematic
TRANSCONDUCTANCE STAGE
The digitally controlled gm section has 42 dB of controllable
gain and makes gain adjustments within each gain range. The
step size resolution ranges from a fine ~ 0.07 dB up to a coarse
6 dB per bit, depending on the gain code. As shown in Figure 39,
of the 42 dB total range, 28 dB has resolution of better than
2 dB, and 22 dB has resolution of better than 1 dB.
Figure 39 shows typical input levels that can be applied to this
amplifier at different gain settings. The maximum input was
determined by finding the 1 dB compression or expansion point
of the VOUT/VSOURCE gain. Note that this is not VOUT/VIN. In this
way, the change in the input impedance of the device is also
taken into account.
0
0.4
0.8
1.2
1.6
2.0
V
OUT
[V
peak]
(V)
2.4
2.8
3.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VSOURCE [V peak] (V)
03692-037
HIGH GAIN
0.1dB GAIN
–5dB GAIN
–8dB GAIN
12dB
GAIN
6dB
GAIN
<2dB
RES
<2dB
RES
<1dB
RES
<1dB
RES
<0.5dB
RESOLUTION
<0.5dB
RES
–11dB GAIN
17dB
GAIN
34dB
GAIN
–25dB GAIN
LOW GAIN
Figure 39. Gain Resolution and Nominal Input and
Output Range over the Gain Range
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