tW0 tWS
參數(shù)資料
型號(hào): AD8556ARZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 11/28頁(yè)
文件大?。?/td> 0K
描述: IC AMP CHOPPER 2MHZ 10MA 8SOIC
標(biāo)準(zhǔn)包裝: 1,000
系列: DigiTrim®
放大器類型: 斷路器(零漂移)
電路數(shù): 1
轉(zhuǎn)換速率: 1.2 V/µs
增益帶寬積: 2MHz
電流 - 輸入偏壓: 49nA
電壓 - 輸入偏移: 2µV
電流 - 電源: 2mA
電流 - 輸出 / 通道: 10mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 140°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
AD8556
Rev. A | Page 19 of 28
CODE
01
0
1
WAVEFORM
tW0
tWS
tW0
tWS
tW0
tWS
tW1
05
44
8-
04
9
Figure 49. Timing Diagram for Code 010011
Table 9. Timing Specifications
Timing Parameter
Description
Specification
tw0
Pulse width for loading 0 into shift register
Between 50 ns and 10 μs
tw1
Pulse width for loading 1 into shift register
≥50 μs
tws
Width between pulses
≥10 μs
Table 10. 38-Bit Serial Word Format
Field No.
Bits
Description
0
0 to 11
12-Bit Start of Packet 1000 0000 0001
1
12 to 13
2-Bit Function
00: Change Sense Current
01: Simulate Parameter Value
10: Program Parameter Value
11: Read Parameter Value
2
14 to 15
2-Bit Parameter
00: Second Stage Gain Code
01: First Stage Gain Code
10: Output Offset Code
11: Other Functions
3
16 to 17
2-Bit Dummy 10
4
18 to 25
8-Bit Value
Parameter 00 (Second Stage Gain Code): 3 LSBs Used
Parameter 01 (First Stage Gain Code): 7 LSBs Used
Parameter 10 (Output Offset Code): All 8 Bits Used
Parameter 11 (Other Functions)
Bit 0 (LSB): Master Fuse
Bit 1: Fuse for Production Test at Analog Devices
Bit 2: Parity Fuse
5
26 to 37
12-Bit End of Packet 0111 1111 1110
A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 μs, the 38-bit serial word transfers
in 2.3 ms. Table 10 summarizes the word format.
Field 0 and Field 5 are the start-of-packet field and end-of-
packet field, respectively. Matching the start-of-packet field with
1000 0000 0001 and the end-of-packet field with 0111 1111
1110 ensures that the serial word is valid and enables decoding
of the other fields.
Field 3 breaks up the data and ensures that no data combination
can inadvertently trigger the start-of-packet and end-of-packet
fields. Field 0 should be written first and Field 5 written last.
Within each field, the MSB must be written first and the LSB
written last. The shift register features power-on reset to minimize
the risk of inadvertent programming; power-on reset occurs
when VDD is between 0.7 V and 2.2 V.
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