參數(shù)資料
型號(hào)： AD8556ARZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 0K
描述： IC AMP CHOPPER 2MHZ 10MA 8SOIC
標(biāo)準(zhǔn)包裝： 1,000
系列： DigiTrim®
放大器類型： 斷路器（零漂移）
電路數(shù)： 1
轉(zhuǎn)換速率： 1.2 V/µs
增益帶寬積： 2MHz
電流 - 輸入偏壓： 49nA
電壓 - 輸入偏移： 2µV
電流 - 電源： 2mA
電流 - 輸出 / 通道： 10mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 140°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
AD8556
Rev. A | Page 21 of 28
Parity Error Detection
A parity check is used to determine whether the programmed
data of an AD8556 is valid, or whether data corruption has
occurred in the nonvolatile memory. Figure 50 shows the
schematic implemented in the AD8556.
VA0 to VA2 is the 3-bit control signal for the second stage gain,
VB0 to VB6 is the 7-bit control signal for the first stage gain,
and VC0 to VC7 is the 8-bit control signal for the output offset.
PFUSE is the signal from the parity fuse, and MFUSE is the
signal from the master fuse.
The function of the 2-input AND gate (Cell AND2) is to ignore
the output of the parity circuit (PAR_SUM signal) when the
master fuse is not blown. PARITY_ERROR is set to 0 when
MFUSE = 0. In the simulation mode, for example, parity check
is disabled. After the master fuse is blown, that is, after the
AD8556 is programmed, the output from the parity circuit
(PAR_SUM signal) is fed to PARITY_ERROR. When
PARITY_ERROR is 0, the AD8556 behaves as a programmed
amplifier. When PARITY_ERROR is 1, a parity error is detected,
and VOUT is connected to VSS.
The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to
VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18).
The output of Cell EOR18 is the DAT_SUM signal. If there is
an even number of 1s in the 18-bit word, DAT_SUM = 0; and if
there is an odd number of 1s in the 18-bit word, DAT_SUM = 1.
See Table 12 for examples.
After the second stage gain, first stage gain, and output offset
are programmed, compute DAT_SUM and set the parity bit
equal to DAT_SUM. If DAT_SUM is 0, the parity fuse should
not be blown in order for the PFUSE signal to be 0. If DAT_SUM is
1, the parity fuse should be blown to set the PFUSE signal to 1.
The code to blow the parity fuse is:
1000 0000 0001 10 11 10 0000 0100 01111111 1110.
After setting the parity bit, the master fuse can be blown to
prevent further programming, using the code:
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110.
Signal PAR_SUM is the output of the 2-input exclusive-OR gate
(Cell EOR2). After the master fuse is blown, set PARITY_ERROR
to PAR_SUM. As previously mentioned, the AD8556 behaves as
a programmed amplifier when PARITY_ERROR = 0 (no parity
error). On the other hand, VOUT is connected to VSS when a
parity error is detected, that is, when PARITY_ERROR = 1.
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
VA0
VA1
VA2
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VC0
VC1
VC2
VC3
VC4
VC5
VC6
VC7
EOR18
OUT
I0
DAT_SUM
PAR_SUM
PFUSE
MFUSE
IN1
IN2
EOR2
AND2
IN1
IN2
PARITY_ERROR
I1
OUT
I2
OUT
0
544
8-
0
50
Figure 50. Functional Circuit of AD8556 Parity Check
Table 12. Examples of DAT_SUM
Second Stage Gain Code
First Stage Gain Code
Output Offset Code
Number of Bits with 1
DAT_SUM
000
000 0000
0000 0000
0
000
000 0000
1000 0000
1
000
000 0000
1000 0001
2
0
000
000 0001
0000 0000
1
000
100 0001
0000 0000
2
0
001
000 0000
0000 0000
1
001
000 0001
1000 0000
3
1
111
111 1111
1111 1111
18
0
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